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[Qemu-ppc] [PULL 2.0 05/15] target-ppc: Define Endian-Correct Accessors

From: Alexander Graf
Subject: [Qemu-ppc] [PULL 2.0 05/15] target-ppc: Define Endian-Correct Accessors for VSR Field Access
Date: Tue, 8 Apr 2014 11:31:44 +0200

From: Tom Musta <address@hidden>

This change defines accessors for VSR doubleword and word fields that
are correct from a host Endian perspective.  This allows code to
use the Power ISA indexing numbers in code.

For example, the xscvdpsxws instruction has a target VSR that looks
like this:

  0           32       64                    127
  | undefined | SW     | undefined | undefined |

VSX helper code will use VsrW(1) to access this field.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
 target-ppc/fpu_helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 691d572..d79aae9 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1782,6 +1782,14 @@ typedef union _ppc_vsr_t {
     float64 f64[2];
 } ppc_vsr_t;
+#define VsrW(i) u32[i]
+#define VsrD(i) u64[i]
+#define VsrW(i) u32[3-(i)]
+#define VsrD(i) u64[1-(i)]
 static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
     if (n < 32) {

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