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[Qemu-ppc] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register nu
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers |
Date: |
Fri, 7 Mar 2014 00:32:11 +0100 |
From: Alexey Kardashevskiy <address@hidden>
Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL - no 32 S
152 00100 11000 CTRL yes - 32 S
This swaps the numbers. No effect from this change is expected though.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 4369e7c..51bcd4a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1250,7 +1250,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_EIE (0x050)
#define SPR_MPC_EID (0x051)
#define SPR_MPC_NRI (0x052)
-#define SPR_CTRL (0x088)
+#define SPR_UCTRL (0x088)
#define SPR_MPC_CMPA (0x090)
#define SPR_MPC_CMPB (0x091)
#define SPR_MPC_CMPC (0x092)
@@ -1259,7 +1259,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_DER (0x095)
#define SPR_MPC_COUNTA (0x096)
#define SPR_MPC_COUNTB (0x097)
-#define SPR_UCTRL (0x098)
+#define SPR_CTRL (0x098)
#define SPR_MPC_CMPE (0x098)
#define SPR_MPC_CMPF (0x099)
#define SPR_MPC_CMPG (0x09A)
--
1.8.1.4
- [Qemu-ppc] [PULL 006/130] target-ppc: remove unsupported SPRs from 970 and P5+, (continued)
- [Qemu-ppc] [PULL 006/130] target-ppc: remove unsupported SPRs from 970 and P5+, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 007/130] KVM: Split QEMUMachine typedef into separate header, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 016/130] target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 014/130] spapr-pci: enable adding PHB via -device, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 012/130] PPC: KVM: fix "set one register", Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 027/130] target-ppc: Add VSX ISA2.06 Multiply Add Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 019/130] target-ppc: Add VSX ISA2.06 xadd/xsub Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 011/130] mmu-hash64: fix Virtual Page Class Key Protection, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 021/130] target-ppc: Add VSX ISA2.06 xdiv Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers,
Alexander Graf <=
- [Qemu-ppc] [PULL 031/130] target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 032/130] target-ppc: Add VSX ISA2.06 Integer Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 054/130] target-ppc: Add ISA2.06 divdeu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt, Alexander Graf, 2014/03/06