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Re: [Qemu-ppc] [V7 PATCH 00/18] target-ppc: VSX Stage 4
From: |
Alexander Graf |
Subject: |
Re: [Qemu-ppc] [V7 PATCH 00/18] target-ppc: VSX Stage 4 |
Date: |
Mon, 27 Jan 2014 16:52:16 +0100 |
On 15.01.2014, at 15:10, Tom Musta <address@hidden> wrote:
> This is the fourth and final series of patches that add emulation support
> to QEMU for the PowerPC Vector Scalar Extension (VSX).
>
> This series adds the instructions that were newly introduced with Power ISA
> V2.07. This includes 3 scalar load instructions, 2 scalar store instructions,
> 7 standard single precision scalar arithmetic instructions, 8 scalar single
> precision fused multiply/add instructions, two integer-to-single-precision
> conversion instructions and 3 vector logical instructions.
>
> The single-precision scalar arithmetic instructions all interpret the most
> significant 64 bits of a VSR as a single precision floating point number
> stored in double precision format (similar to the standard PowerPC floating
> point single precision instructions). Thus a common theme in the supporting
> code is rounding of an intermediate double-precision number to single
> precision.
Thanks, applied all to ppc-next.
Alex
- [Qemu-ppc] [V7 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, (continued)
- [Qemu-ppc] [V7 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Tom Musta, 2014/01/15
- [Qemu-ppc] [V7 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Tom Musta, 2014/01/15
- [Qemu-ppc] [V7 PATCH 15/18] target-ppc: Move To/From VSR Instructions, Tom Musta, 2014/01/15
- [Qemu-ppc] [V7 PATCH 17/18] target-ppc: Scalar Round to Single Precision, Tom Musta, 2014/01/15
- [Qemu-ppc] [V7 PATCH 16/18] target-ppc: Floating Merge Word Instructions, Tom Musta, 2014/01/15
- [Qemu-ppc] [V7 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions, Tom Musta, 2014/01/15
- Re: [Qemu-ppc] [V7 PATCH 00/18] target-ppc: VSX Stage 4,
Alexander Graf <=