Re: [Qemu-ppc] [Qemu-devel] [V3 PATCH 09/14] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions

[Richard Henderson]

On 12/18/2013 12:49 PM, Tom Musta wrote:
> +#define FPU_FCFI(op, cvtr, is_single)                 \
> +uint64_t helper_##op(CPUPPCState *env, uint64_t arg)  \
> +{                                                     \
> +    CPU_DoubleU farg;                                 \
> +                                                      \
> +    farg.d = cvtr(arg, &env->fp_status);              \
> +                                                      \
> +    if (is_single) {                                  \
> +        farg.d = helper_frsp(env, farg.d);            \
> +    }                                                 \
> +    helper_float_check_status(env);                   \
> +    return farg.ll;                                   \
> +}

This formulation will lead to double-rounding errors for some int64 inputs.
You should convert to single-precision directly, then convert to double.


r~