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[Qemu-ppc] [PATCH 29/30] target-ppc: emulate store doubleword pair instr
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 29/30] target-ppc: emulate store doubleword pair instructions |
Date: |
Fri, 26 Apr 2013 20:21:48 +0200 |
From: Aurelien Jarno <address@hidden>
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 62f9309..aba7e3f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3452,6 +3452,52 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
/* stfs stfsu stfsux stfsx */
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
+/* stfdp */
+static void gen_stfdp(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_imm_index(ctx, EA, 0); \
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ } else {
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ }
+ tcg_temp_free(EA);
+}
+
+/* stfdpx */
+static void gen_stfdpx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ } else {
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ }
+ tcg_temp_free(EA);
+}
+
/* Optional: */
static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv
arg2)
{
@@ -9099,6 +9145,8 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
+GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
#undef GEN_CRLOGIC
#define GEN_CRLOGIC(name, tcg_op, opc) \
--
1.6.0.2
- [Qemu-ppc] [PATCH] Fix PReP NIP reset value, (continued)
- [Qemu-ppc] [PATCH] Fix PReP NIP reset value, Fabien Chouteau, 2013/04/30
- Re: [Qemu-ppc] [PATCH] Fix PReP NIP reset value, Alexander Graf, 2013/04/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH] Fix PReP NIP reset value, Fabien Chouteau, 2013/04/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH] Fix PReP NIP reset value, Alexander Graf, 2013/04/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH] Fix PReP NIP reset value, Fabien Chouteau, 2013/04/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH] Fix PReP NIP reset value, Alexander Graf, 2013/04/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH] Fix PReP NIP reset value, Hervé Poussineau, 2013/04/30
[Qemu-ppc] [PATCH 20/30] PPC: Fix dcbz for linux-user on 970, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 22/30] disas: Disassemble all ppc insns for the guest, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 23/30] target-ppc: add instruction flags for Book I 2.05, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 29/30] target-ppc: emulate store doubleword pair instructions,
Alexander Graf <=
[Qemu-ppc] [PATCH 24/30] target-ppc: emulate cmpb instruction, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 28/30] target-ppc: emulate load doubleword pair instructions, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 26/30] target-ppc: emulate fcpsgn instruction, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 25/30] target-ppc: emulate prtyw and prtyd instructions, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 21/30] target-ppc: optimize fabs, fnabs, fneg, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 19/30] powerpc: correctly handle fpu exceptions., Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 27/30] target-ppc: emulate lfiwax instruction, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 15/30] pseries: Fix some small errors in XICS logic, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 14/30] target-ppc: Add more stubs for POWER7 PMU registers, Alexander Graf, 2013/04/26
[Qemu-ppc] [PATCH 18/30] pseries: Generate device paths for VIO devices, Alexander Graf, 2013/04/26