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[Qemu-ppc] [PATCH v2 03/10] target-ppc: add instruction flags for Book I
From: |
Aurelien Jarno |
Subject: |
[Qemu-ppc] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05 |
Date: |
Sat, 20 Apr 2013 20:56:15 +0200 |
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-ppc/cpu.h | 4 +++-
target-ppc/translate_init.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 42c36e2..8b0b651 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1870,8 +1870,10 @@ enum {
PPC2_PRCNTL = 0x0000000000000008ULL,
/* Byte-reversed, indexed, double-word load and store */
PPC2_DBRX = 0x0000000000000010ULL,
+ /* Book I 2.05 PowerPC specification */
+ PPC2_ISA205 = 0x0000000000000020ULL,
-#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 781170f..14f6599 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7014,7 +7014,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.7.10.4
- [Qemu-ppc] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instructions, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 09/10] target-ppc: emulate store doubleword pair instructions, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05,
Aurelien Jarno <=
- [Qemu-ppc] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 02/10] disas: Disassemble all ppc insns for the guest, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 04/10] target-ppc: emulate cmpb instruction, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 01/10] target-ppc: optimize fabs, fnabs, fneg, Aurelien Jarno, 2013/04/20
- [Qemu-ppc] [PATCH v2 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms, Aurelien Jarno, 2013/04/20
- Re: [Qemu-ppc] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Alexander Graf, 2013/04/26