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Re: [Qemu-ppc] [Qemu-devel] KVM call minutes 2013-01-29 - Port I/O


From: Markus Armbruster
Subject: Re: [Qemu-ppc] [Qemu-devel] KVM call minutes 2013-01-29 - Port I/O
Date: Wed, 30 Jan 2013 14:09:20 +0100
User-agent: Gnus/5.13 (Gnus v5.13) Emacs/24.1 (gnu/linux)

Peter Maydell <address@hidden> writes:

> On 30 January 2013 11:39, Andreas Färber <address@hidden> wrote:
>> Proposal by hpoussin was to move _list_add() code to ISADevice:
>> http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg00508.html
>>
>> Concerns:
>> * PCI devices (VGA, QXL) register I/O ports as well
>>   => above patches add dependency on ISABus to machines
>>      -> "<benh> no mac ever had one"
>>   => PCIDevice shouldn't use ISA API with NULL ISADevice
>> * Lack of avi: Who decides about memory API these days?
>>
>> armbru and agraf concluded that moving this into ISA is wrong.
>>
>> => I will drop the remaining ioport patches from above series.
>>
>> Suggestions on how to proceed with tackling the issue are welcome.
>
> How does this stuff work on real hardware? I would have
> expected that a PCI device registering the fact it has
> IO ports would have to do so via the PCI controller it
> is plugged into...
>
> My naive don't-know-much-about-portio suggestion is that this
> should work the same way as memory regions: each device
> provides portio regions, and the controller for the bus
> (ISA or PCI) exposes those to the next layer up, and
> something at board level maps it all into the right places.

Makes sense me, but I'm naive, too :)

For me, "I/O ports" are just an alternate address space some devices
have.  For instance, x86 CPUs have an extra pin for selecting I/O
vs. memory address space.  The ISA bus has separate read/write pins for
memory and I/O.

This isn't terribly special.  Mapping address spaces around is what
devices bridging buses do.

I'd expect a system bus for an x86 CPU to have both a memory and an I/O
address space.

I'd expect an ISA PC's sysbus - ISA bridge to map both directly.

I'd expect an ISA bridge for a sysbus without a separate I/O address
space to map the ISA I/O address space into the sysbus's normal address
space somehow.

PCI ISA bridges have their own rules, but I've gotten away with ignoring
the details so far :)



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