Re: [Qemu-ppc] [PATCH] PPC: Bring EPR support closer to reality

[Scott Wood]

On 01/07/2013 11:50:02 AM, Alexander Graf wrote:
> >> @@ -1407,6 +1425,9 @@ static int openpic_init(SysBusDevice *dev)
> >>         opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
> >>         opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
> >>         opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
> >> +        /* XXX really only available as of MPIC 4.0 */
> >> +        opp->mpic_mode_mask = GCR_MODE_PROXY;
> >> +
> >
> > Shouldn't mpic_mode_mask be set to GCR_MODE_MIXED for Raven?
>
> Does Raven support the MIXED bit?

Yes.  It's part of the base openpic spec (though it calls the bit "8259  
pass through disable").

> Do you have a pointer to the spec?

http://www.slac.stanford.edu/grp/cd/soft/vxworks/doc/cpu/pci/ppc/mcp750/mcp750pg.pdf

-Scott