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[Qemu-ppc] [PATCH 02/16] target-ppc: Rework storage of VPA registration
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 02/16] target-ppc: Rework storage of VPA registration state |
Date: |
Tue, 30 Oct 2012 14:24:58 +1100 |
With PAPR guests, hypercalls allow registration of the Virtual Processor
Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow
for certain communication between the guest and hypervisor. Currently, we
store the addresses of the three areas and the size of the dtl in
CPUPPCState.
The SLB shadow and DTL are variable sized, with the size being retrieved
from within the registered memory area at the hypercall time. This size
can later be overwritten with other information, however, so we need to
save the size as of registration time. We already do this for the DTL,
but not for the SLB shadow, so this patch fixes that.
In addition, we change the storage of the VPA information to use fixed
size integer types which will make life easier for syncing this data with
KVM, which we will need in future.
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 286f42a..e603d9f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1045,9 +1045,9 @@ struct CPUPPCState {
#endif
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
- hwaddr vpa_addr;
- hwaddr slb_shadow_addr, slb_shadow_size;
- hwaddr dtl_addr, dtl_size;
+ uint64_t vpa_addr;
+ uint64_t slb_shadow_addr, slb_shadow_size;
+ uint64_t dtl_addr, dtl_size;
#endif /* TARGET_PPC64 */
int error_code;
--
1.7.10.4
- [Qemu-ppc] [PATCH 04/16] pseries: Clean up inconsistent variable name in xics.c, (continued)
- [Qemu-ppc] [PATCH 04/16] pseries: Clean up inconsistent variable name in xics.c, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 06/16] pseries: Cleanup duplications of ics_valid_irq() code, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 12/16] target-pcc: Convert ppcemb_tlb_t to use fixed 64-bit RPN, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 16/16] pseries: Generate unique LIOBNs for PCI host bridges, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 10/16] pseries: Add tracepoints to the XICS interrupt controller, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 07/16] pseries: Move XICS initialization before cpu initialization, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 15/16] pseries: Fix bug in PCI MSI allocation, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 05/16] pseries: Use #define for XICS base irq number, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 03/16] target-ppc: Extend FPU state for newer POWER CPUs, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 11/16] pseries: Split xics irq configuration from state information, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 02/16] target-ppc: Rework storage of VPA registration state,
David Gibson <=
- [Qemu-ppc] [PATCH 13/16] pseries: Implement PAPR NVRAM, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 08/16] pseries: Return the token when we register an RTAS call, David Gibson, 2012/10/29
- [Qemu-ppc] [PATCH 14/16] pseries: Update SLOF for NVRAM support, David Gibson, 2012/10/29