[Qemu-ppc] slbfee instruction for power7

[Liang Guo]

Hi, List,

I'm trying to impliment slbfee instruction for power7, but have some
trouble with it.

This is my git diff against agraf's aix branch:

address@hidden:~/git/qemu/agraf(aix) $ git diff ppc-dis.c
target-ppc/helper.h target-ppc/helper.c target-ppc/op_helper.c
target-ppc/translate.c
diff --git a/ppc-dis.c b/ppc-dis.c
index ffdbec1..15e71d9 100644
--- a/ppc-dis.c
+++ b/ppc-dis.c
@@ -4531,6 +4531,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {

 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },

+{ "slbfee",  X(31,979), XRA_MASK,      PPC64,          { RT, RB } },
+
 { "stwcix",  X(31,917),        X_MASK,         POWER6,         { RS,
RA0, RB } },

 { "sthbrx",  X(31,918),        X_MASK,         COM,            { RS,
RA0, RB } },
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 928fbcf..bc0396b 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -815,6 +815,20 @@ int ppc_load_slb_vsid (CPUPPCState *env,
target_ulong rb, target_ulong *rt)
     *rt = slb->vsid;
     return 0;
 }
+
+int ppc_slb_find_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
+{
+    slb = slb_lookup(env, rb);
+    if (!slb) {
+        *rt = 0;
+       /*set cr0 */
+    }
+    *rt = slb->vsid;
+    /* set cr0 */
+}
+
+
+
 #endif /* defined(TARGET_PPC64) */

 /* Perform segment based translation */
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 148543a..322e8b1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -351,6 +351,7 @@ DEF_HELPER_FLAGS_1(tlbie, TCG_CALL_CONST, void, tl)
 DEF_HELPER_FLAGS_2(store_slb, TCG_CALL_CONST, void, tl, tl)
 DEF_HELPER_1(load_slb_esid, tl, tl)
 DEF_HELPER_1(load_slb_vsid, tl, tl)
+DEF_HELPER_1(slb_find_esid, tl, tl)
 DEF_HELPER_FLAGS_0(slbia, TCG_CALL_CONST, void)
 DEF_HELPER_FLAGS_1(slbie, TCG_CALL_CONST, void, tl)
 #endif
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3f4e067..3f55a3d 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -3785,6 +3785,16 @@ target_ulong helper_load_slb_vsid (target_ulong rb)
     return rt;
 }

+target_ulong helper_slb_find_esid (target_ulong rb)
+{
+    target_ulong rt;
+
+    if (ppc_slb_find_esid(env, rb, &rt) < 0) {
+        helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL);
+    }
+    return rt;
+}
+
 void helper_slbia (void)
 {
     ppc_slb_invalidate_all(env);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b2780db..a1dc9e9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -309,7 +309,11 @@ static inline void gen_debug_exception(DisasContext *ctx)

 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
 {
-    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
+    FILE* oplog = fopen("/tmp/oplog.txt", "a");
+    //printf("\nOpcode: %x\n", ctx->opcode);
+    fprintf(oplog, "di %x\n", ctx->opcode);
+    fclose(oplog);
+    //gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
 }

 /* Stop translation */
@@ -4325,6 +4329,21 @@ static void gen_slbmfev(DisasContext *ctx)
                              cpu_gpr[rB(ctx->opcode)]);
 #endif
 }
+
+static void gen_slbfee(DisasContext *ctx)
+{
+#if defined(CONFIG_USER_ONLY)
+    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+    if (unlikely(!ctx->mem_idx)) {
+        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+        return;
+    }
+    gen_helper_slb_find_esid(cpu_gpr[rS(ctx->opcode)],
+                             cpu_gpr[rB(ctx->opcode)]);
+#endif
+}
+
 #endif /* defined(TARGET_PPC64) */

 /***                      Lookaside buffer management                      ***/
@@ -8541,6 +8560,7 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12,
0x07, 0x001F0001,
 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
+GEN_HANDLER2(slbfee, "slbfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
 #endif
 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),


Most part are copied from slbmfev instruction, but some part are not
correctly implimented :

1) slbfee set CR0 according the result of slb_lookup, how can CR0 be seted?

2) GEN_HANDLER2 have 4 hex code parameter, what's the meaning of these
hex code, how can I find related hex code for slbfee instruction ?

Thanks,
-- 
Liang Guo
http://bluestone.cublog.cn