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Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value wit

From: Mark Cave-Ayland
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.
Date: Fri, 06 Apr 2012 19:56:22 +0100
User-agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv: Gecko/20120317 Icedove/3.0.11

On 29/03/12 20:06, Scott Wood wrote:

Hrm, yeah.  I think what you ought to do is to use the new logic just
for the "classic" exception models.  Have the default branch remain
the one that just masks ME.  That's wrong, but it's the same wrong as
we have already, and we can fix it later once we've verified what the
right thing to do is for 40x and BookE.

Agreed. I've just reworked the patch based on yours/David's comments so that it should minimise the effect of any changes.

I'm actually coming at this from a fixing what was potentially an
OpenBIOS bug rather than a PPC angle, so I have to admit I have no I
idea which ones are the "classic" exception models. Would you consider
this to be just EXCP_STD, EXCP_6* and EXCP_7*?

Also POWERPC_EXCP_G2, and maybe POWERPC_EXCP_970?  Even on server
there's a question of whether it's a 2.06 chip or previous version of
the architecture.

One thing that sticks out for classic chips that is missing here is
MSR[POW], which should be cleared on exceptions.

I'm not sure about _970 given that it's 64-bit, so I've left this on the old behaviour for the time being and altered the patch so that MSR_POW is now cleared in the classic exception path too.

I see that Andreas has already applied the second patch in the series to ppc-next, so I'll just resubmit a revised version of the first patch shortly.



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