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Re: [Qemu-ppc] [PATCH] Set an invalid-bits mask for each SPE instruction
Re: [Qemu-ppc] [PATCH] Set an invalid-bits mask for each SPE instructions
Fri, 07 Oct 2011 14:40:47 +0200
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On 09/28/2011 05:54 PM, Fabien Chouteau wrote:
SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
for the first instruction, but the second one can have a different mask.
GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000,
Signed-off-by: Fabien Chouteau<address@hidden>
It certainly doesn't make the code more ugly than it was before :).
Applied to my local ppc-next branch. I take it that you verified all the
invalid masks are sane.
There are some lines exceeding 80 characters, but I'm fairly sure they
did before too. So I'll let this slip through for the sake of readability.
- Re: [Qemu-ppc] [PATCH] Set an invalid-bits mask for each SPE instructions,
Alexander Graf <=