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Re: Using All Cores of CPU on Snapdragon Processor during x86-to-ARM Use
Re: Using All Cores of CPU on Snapdragon Processor during x86-to-ARM User Space Emulation
Wed, 13 May 2020 11:02:11 +0100
mu4e 1.4.5; emacs 28.0.50
Vijay Daita <address@hidden> writes:
> It is my understanding that one would be unable to do x86-to-ARM user space
> emulation while utilizing all cores because of x86 barriers.
Actually the utilisation of multiple cores (often referred to at MTTCG)
is a function of system emulation and you are correct for x86-on-ARM we
don't enable MTTCG because we don't currently add barrier instructions
to fully emulate the x86 memory model. However for linux-user we have
always followed the guest threading model because the guest clone() is
passed down to the host. However because the memory modelling isn't
perfect you can run into problems because of the mismatch.
> I wanted to
> know if there is difference between what QEMU aims to do and using a
> interpreter of sorts to convert x86 instructions directly to ARM
> instructions so that when run on the system directly, the system can
> decide, itself, how to apportion the task.
This is what the TCG does - it translates guest instructions into groups
of host instructions. We could insert the extra barriers for all loads
and stores but the effect would be to cripple performance. In an ideal
world we would only do these for the load/store instructions involved in
inter-thread synchronisation operations but that's a fairly tricky
problem to solve.
> I am new to this, so sorry if
> this doesn't make very much sense.
> Thank you