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Re: [Qemu-discuss] [Qemu-devel] IRQ per CPU

From: Stefan Hajnoczi
Subject: Re: [Qemu-discuss] [Qemu-devel] IRQ per CPU
Date: Wed, 11 Jul 2018 13:49:26 +0100
User-agent: Mutt/1.10.0 (2018-05-17)

On Thu, Jul 05, 2018 at 03:16:44PM +0800, Dongli Zhang wrote:
> On 07/05/2018 12:12 PM, Probir Roy wrote:
> >> Does 'per CPU basis' indicates irq per cpu, or irq per device queue?
> > 
> > IRQ per CPU core, meaning that IRQ will be raised at and served by
> > that CPU. Does IRQ per queue mean the same thing?
> > 
> About 'IRQ per queue', the device may create multiple queue in the OS driver.
> The number of queues are always proportional to the number of CPU core/thread
> (although this is also always configurable by OS driver).
> Usually the per-queue irq/vector is bound to each CPU. As the number of
> queue/irq is always the same as the number of CPU, it is sort of 'per CPU
> basis', as each CPU will be serving irq for its own queue.

Some more background on devices with multiple irqs:

It's the guest kernel that configures interrupt routing on modern
systems where the interrupt controller hardware supports that.

With a PCI device you would need multiple Message-Signalled Interrupt
vectors.  Then the guest driver can set the irq affinity so that the
vcpu of your choice receives each of these interrupts.

Interrupts are a limited resource, even when using Message-Signalled
Interrupts, so you'll have to choose a maximum number of interrupts that
the device supports.



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