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Re: [Qemu-discuss] Where are local APIC addresses in QEMU?


From: Peter Maydell
Subject: Re: [Qemu-discuss] Where are local APIC addresses in QEMU?
Date: Fri, 4 Nov 2016 11:37:11 +0000

On 4 November 2016 at 05:09, Tu Do 2 <address@hidden> wrote:
> Hi list,
>
> I'm doing some LAPIC programing.
>
> According to Intel's document, FEE0 0000H to FEE0 03F0H is the range of
> local APIC. However, examining it from QEMU console, I can only find the
> value 0 there:
>
>     (qemu) x/128b 0xfee00000
>     fee00000: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00008: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00018: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00020: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00028: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00038: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00048: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00050: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00058: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00060: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00068: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00070: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>     fee00078: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
>
> I checked 128 bytes to see if anything different than 0. At least, FEE0
> 0030H should contain a different value since it is where APIC version is in.

Trying to read from hardware devices via GDB or the
qemu console's memory read commands is not necessarily
going to work very well. For instance many hardware devices
insist on 32-bit accesses (no byte reads) whereas gdb may
be doing byte reads. If you try to do a read of a register
which has "affects behaviour of device on read" then you'll
confuse it. And so on. I don't know if the LAPIC in
particular is subject to this kind of thing but I wouldn't
be surprised to find it was. Basically the memory read
and write operations are intended to work on memory (RAM
or ROM), not devices.

thanks
-- PMM



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