We have a multi-core network processor system, wherein we run a multi-threaded (using pthreads) program. We have the pthreads pinned to hw cores (fixed pinning/mapping). We would like to emulate / simulate such
We have built a C++ simulator wherein we use a internally developed ISS (instruction set simulator). We create as many ISS instances as many cores we have and then have a shared memory system around it.. Our
ISS is interpreted, ie each instruction in our ISA (instruction set architecture) is implemented in C++.
We have already used Qemu to simulate a single core - we have built a library that defines the mapping from our ISA to x86 and qemu uses this to do dynamic translation.. but I would like to know if it is possible
to simulate multi-core system.