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Re: [PATCH v3 72/97] target/arm: Implement SME2 SEL
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v3 72/97] target/arm: Implement SME2 SEL |
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Date: |
Thu, 3 Jul 2025 13:21:55 +0100 |
On Wed, 2 Jul 2025 at 13:38, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/helper-sme.h | 5 +
> target/arm/tcg/sme_helper.c | 315 +++++++++++++++++++++++++++++++++
> target/arm/tcg/translate-sme.c | 31 ++++
> target/arm/tcg/sme.decode | 9 +
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v3 68/97] target/arm: Implement SVE2p1 WHILE (predicate as counter), (continued)
- [PATCH v3 57/97] target/arm: Enable SCLAMP, UCLAMP for SVE2p1, Richard Henderson, 2025/07/02
- [PATCH v3 55/97] target/arm: Implement SME2 ZIP, UZP (two registers), Richard Henderson, 2025/07/02
- [PATCH v3 58/97] target/arm: Implement FCLAMP for SME2, SVE2p1, Richard Henderson, 2025/07/02
- [PATCH v3 64/97] target/arm: Move scale by esz into helper_sve_while*, Richard Henderson, 2025/07/02
- [PATCH v3 72/97] target/arm: Implement SME2 SEL, Richard Henderson, 2025/07/02
- Re: [PATCH v3 72/97] target/arm: Implement SME2 SEL,
Peter Maydell <=
- [PATCH v3 77/97] target/arm: Implement DUPQ for SME2p1/SVE2p1, Richard Henderson, 2025/07/02
- [PATCH v3 59/97] target/arm: Implement SME2p1 Multiple Zero, Richard Henderson, 2025/07/02
- [PATCH v3 49/97] target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU, Richard Henderson, 2025/07/02
- [PATCH v3 67/97] target/arm: Implement SVE2p1 WHILE (predicate pair), Richard Henderson, 2025/07/02
- [PATCH v3 65/97] target/arm: Split trans_WHILE to lt and gt, Richard Henderson, 2025/07/02