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[PATCH 14/22] target/riscv: convert ibex CPU models to RISCVCPUDef
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From: |
Paolo Bonzini |
|
Subject: |
[PATCH 14/22] target/riscv: convert ibex CPU models to RISCVCPUDef |
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Date: |
Fri, 28 Feb 2025 11:27:38 +0100 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 39 ++++++++++++++++-----------------------
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 049d3f90f47..fc5bf6def8c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -688,28 +688,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
}
-
-static void rv32_ibex_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_12_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
- cpu->cfg.ext_smepmp = true;
-
- cpu->cfg.ext_zba = true;
- cpu->cfg.ext_zbb = true;
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbs = true;
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3050,7 +3028,22 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV32,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32,
rv32_ibex_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVI | RVM | RVC | RVU,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .cfg.max_satp_mode = VM_1_10_MBARE,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true,
+ .cfg.ext_smepmp = true,
+
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbs = true
+ ),
+
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV32
),
--
2.48.1
- [PATCH 03/22] target/riscv: introduce RISCVCPUDef, (continued)
- [PATCH 03/22] target/riscv: introduce RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class, Paolo Bonzini, 2025/02/28
- [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file, Paolo Bonzini, 2025/02/28
- [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional, Paolo Bonzini, 2025/02/28
- [PATCH 07/22] target/riscv: add more RISCVCPUDef fields, Paolo Bonzini, 2025/02/28
- [PATCH 11/22] target/riscv: convert bare CPU models to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 12/22] target/riscv: convert dynamic CPU models to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 14/22] target/riscv: convert ibex CPU models to RISCVCPUDef,
Paolo Bonzini <=
- [PATCH 17/22] target/riscv: generalize custom CSR functionality, Paolo Bonzini, 2025/02/28
- [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function, Paolo Bonzini, 2025/02/28
- [PATCH 13/22] target/riscv: convert SiFive E CPU models to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 15/22] target/riscv: convert SiFive U models to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive, Paolo Bonzini, 2025/02/28
- [PATCH 19/22] target/riscv: convert TT Ascalon to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 22/22] target/riscv: remove .instance_post_init, Paolo Bonzini, 2025/02/28
- [PATCH 20/22] target/riscv: convert Ventana V1 to RISCVCPUDef, Paolo Bonzini, 2025/02/28
- [PATCH 21/22] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef, Paolo Bonzini, 2025/02/28