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[PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCES
From: |
Peter Maydell |
Subject: |
[PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED |
Date: |
Thu, 20 Feb 2025 16:20:54 +0000 |
CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description
of what this return value from a cpreg accessfn does, but it's liable
to confusion because it doesn't match how the Arm ARM pseudocode
indicates this case. What it does is an EXCP_UDEF with a zero
("uncategorized") syndrome value, which is what an UNDEFINED instruction
does. The pseudocode uses "UNDEFINED" to show this; rename our
constant to CP_ACCESS_UNDEFINED to make the parallel clearer.
Commit created with
sed -i -e 's/CP_ACCESS_TRAP_UNCATEGORIZED/CP_ACCESS_UNDEFINED/' $(git grep -l
CP_ACCESS_TRAP_UNCATEGORIZED)
plus manual editing of the comment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-14-peter.maydell@linaro.org
---
target/arm/cpregs.h | 5 +++--
target/arm/helper.c | 30 +++++++++++++++---------------
target/arm/tcg/op_helper.c | 6 +++---
3 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fb3b84baa1e..52377c6eb50 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -337,13 +337,14 @@ typedef enum CPAccessResult {
CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3,
/*
- * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+ * Access fails with UNDEFINED, i.e. an exception syndrome 0x0
+ * ("uncategorized"), which is what an undefined insn produces.
* Note that this is not a catch-all case -- the set of cases which may
* result in this failure is specifically defined by the architecture.
* This trap is always to the usual target EL, never directly to a
* specified target EL.
*/
- CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+ CP_ACCESS_UNDEFINED = (2 << 2),
} CPAccessResult;
/* Indexes into fgt_read[] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index aacb53d31a2..71dead7241b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -285,7 +285,7 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
{
if (!is_a64(env) && arm_current_el(env) == 3 &&
arm_is_secure_below_el3(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -310,7 +310,7 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState
*env,
return CP_ACCESS_TRAP_EL3;
}
/* This will be EL1 NS and EL2 NS, which just UNDEF */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
/*
@@ -2246,7 +2246,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env,
const ARMCPRegInfo *ri,
if (!isread && ri->state == ARM_CP_STATE_AA32 &&
arm_is_secure_below_el3(env)) {
/* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
break;
case 2:
@@ -2255,7 +2255,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env,
const ARMCPRegInfo *ri,
}
if (!isread && el < arm_highest_el(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
@@ -2385,7 +2385,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
switch (arm_current_el(env)) {
case 1:
if (!arm_is_secure(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
if (!(env->cp15.scr_el3 & SCR_ST)) {
return CP_ACCESS_TRAP_EL3;
@@ -2393,7 +2393,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
return CP_ACCESS_OK;
case 0:
case 2:
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
case 3:
return CP_ACCESS_OK;
default:
@@ -3304,7 +3304,7 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
}
return CP_ACCESS_TRAP_EL3;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
}
return CP_ACCESS_OK;
@@ -3601,7 +3601,7 @@ static CPAccessResult at_e012_access(CPUARMState *env,
const ARMCPRegInfo *ri,
* scr_write() ensures that the NSE bit is not set otherwise.
*/
if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -3611,7 +3611,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env,
const ARMCPRegInfo *ri,
{
if (arm_current_el(env) == 3 &&
!(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return at_e012_access(env, ri, isread);
}
@@ -4684,7 +4684,7 @@ static CPAccessResult sp_el0_access(CPUARMState *env,
const ARMCPRegInfo *ri,
* Access to SP_EL0 is undefined if it's being used as
* the stack pointer.
*/
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -5674,7 +5674,7 @@ static CPAccessResult sel2_access(CPUARMState *env, const
ARMCPRegInfo *ri,
if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) {
return CP_ACCESS_OK;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
@@ -5710,7 +5710,7 @@ static CPAccessResult nsacr_access(CPUARMState *env,
const ARMCPRegInfo *ri,
if (isread) {
return CP_ACCESS_OK;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
static const ARMCPRegInfo el3_cp_reginfo[] = {
@@ -5798,7 +5798,7 @@ static CPAccessResult e2h_access(CPUARMState *env, const
ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -5896,7 +5896,7 @@ static CPAccessResult el2_e2h_e12_access(CPUARMState *env,
}
/* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
if (ri->orig_accessfn) {
return ri->orig_accessfn(env, ri->opaque, isread);
@@ -6751,7 +6751,7 @@ static CPAccessResult access_lor_other(CPUARMState *env,
{
if (arm_is_secure_below_el3(env)) {
/* UNDEF if SCR_EL3.NS == 0 */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return access_lor_ns(env, ri, isread);
}
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index fcee11e29ad..2230351a8f4 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -764,7 +764,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env,
uint32_t key,
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
- res = CP_ACCESS_TRAP_UNCATEGORIZED;
+ res = CP_ACCESS_UNDEFINED;
goto fail;
}
@@ -869,8 +869,8 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env,
uint32_t key,
case CP_ACCESS_TRAP_EL2:
case CP_ACCESS_TRAP_EL1:
break;
- case CP_ACCESS_TRAP_UNCATEGORIZED:
- /* CP_ACCESS_TRAP_UNCATEGORIZED is never direct to a specified EL */
+ case CP_ACCESS_UNDEFINED:
+ /* CP_ACCESS_UNDEFINED is never direct to a specified EL */
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
arm_cpreg_in_idspace(ri)) {
/*
--
2.43.0
- [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64(), (continued)
- [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64(), Peter Maydell, 2025/02/20
- [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult, Peter Maydell, 2025/02/20
- [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps, Peter Maydell, 2025/02/20
- [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling, Peter Maydell, 2025/02/20
- [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1, Peter Maydell, 2025/02/20
- [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition, Peter Maydell, 2025/02/20
- [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping, Peter Maydell, 2025/02/20
- [PULL 17/41] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs, Peter Maydell, 2025/02/20
- [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs, Peter Maydell, 2025/02/20
- [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL, Peter Maydell, 2025/02/20
- [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED,
Peter Maydell <=
- [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs, Peter Maydell, 2025/02/20
- [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs, Peter Maydell, 2025/02/20
- [PULL 20/41] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs, Peter Maydell, 2025/02/20
- [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs, Peter Maydell, 2025/02/20
- [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX, Peter Maydell, 2025/02/20
- [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm(), Peter Maydell, 2025/02/20
- [PULL 25/41] roms: Update vbootrom to 1287b6e, Peter Maydell, 2025/02/20
- [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU, Peter Maydell, 2025/02/20
- [PULL 26/41] pc-bios: Add NPCM8XX vBootrom, Peter Maydell, 2025/02/20
- [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr, Peter Maydell, 2025/02/20