Re: [PATCH v5 5/7] target/riscv: Add CTR sctrclr instruction.

[Alistair Francis]

On Thu, Dec 5, 2024 at 9:35 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> CTR extension adds a new instruction sctrclr to quickly
> clear the recorded entries buffer.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h                             |  1 +
>  target/riscv/cpu_helper.c                      |  7 +++++++
>  target/riscv/helper.h                          |  1 +
>  target/riscv/insn32.decode                     |  1 +
>  target/riscv/insn_trans/trans_privileged.c.inc | 11 ++++++++++
>  target/riscv/op_helper.c                       | 29 
> ++++++++++++++++++++++++++
>  6 files changed, 50 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 
> f39ca48d37332c4e5907ca87040de420f78df2e4..85ca2bfe435d0c9d245f2690fe3bde3e076d3b2f
>  100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -613,6 +613,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong 
> newpriv, bool virt_en);
>
>  void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long 
> dst,
>      enum CTRType type, target_ulong prev_priv, bool prev_virt);
> +void riscv_ctr_clear(CPURISCVState *env);
>
>  void riscv_translate_init(void);
>  G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 
> dbdad4e29d7de0713f7530c46e9fab03d3c459a4..b1130180710b0e01e8ebe33f0974edd8d5abe56d
>  100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -783,6 +783,13 @@ static void riscv_ctr_freeze(CPURISCVState *env, 
> uint64_t freeze_mask,
>      }
>  }
>
> +void riscv_ctr_clear(CPURISCVState *env)
> +{
> +    memset(env->ctr_src, 0x0, sizeof(env->ctr_src));
> +    memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst));
> +    memset(env->ctr_data, 0x0, sizeof(env->ctr_data));
> +}
> +
>  static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
>  {
>      switch (priv) {
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 
> 820ddccf92ab07cbe80ae03b3d2d2ccc4f8e4765..011ee628f81333e30cfa7a375788e546965e4b30
>  100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
>  #ifndef CONFIG_USER_ONLY
>  DEF_HELPER_1(sret, tl, env)
>  DEF_HELPER_1(mret, tl, env)
> +DEF_HELPER_1(ctr_clear, void, env)
>  DEF_HELPER_1(wfi, void, env)
>  DEF_HELPER_1(wrs_nto, void, env)
>  DEF_HELPER_1(tlb_flush, void, env)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 
> a2b4c0ddd47ad9464b4b180fb19e6a3b64dbe4e5..8188113bcc90482733f676227858829bac5c5462
>  100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -114,6 +114,7 @@
>  # *** Privileged Instructions ***
>  ecall       000000000000     00000 000 00000 1110011
>  ebreak      000000000001     00000 000 00000 1110011
> +sctrclr     000100000100     00000 000 00000 1110011
>  uret        0000000    00010 00000 000 00000 1110011
>  sret        0001000    00010 00000 000 00000 1110011
>  mret        0011000    00010 00000 000 00000 1110011
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc 
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 
> b19d692c22dc74c41df72dae99448c37a0216980..a67088d25bade5cb3be62647e411045894bffe33
>  100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -69,6 +69,17 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
>      return true;
>  }
>
> +static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
> +        gen_helper_ctr_clear(tcg_env);
> +        return true;
> +    }
> +#endif
> +    return false;
> +}
> +
>  static bool trans_uret(DisasContext *ctx, arg_uret *a)
>  {
>      return false;
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 
> 0684a27bfdb72f6fc5945f30500c2e3a95e85e2f..e7301ee8ca2e3145396a274126e591921b6d9e01
>  100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -389,6 +389,35 @@ void helper_ctr_add_entry(CPURISCVState *env, 
> target_ulong src,
>                          env->priv, env->virt_enabled);
>  }
>
> +void helper_ctr_clear(CPURISCVState *env)
> +{
> +    /*
> +     * It's safe to call smstateen_acc_ok() for umode access regardless of 
> the
> +     * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the 
> bit
> +     * is zero, smstateen_acc_ok() will return the correct exception code and
> +     * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that
> +     * scenario the U-mode check below will handle that case.
> +     */
> +    RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
> +    if (ret != RISCV_EXCP_NONE) {
> +        riscv_raise_exception(env, ret, GETPC());
> +    }
> +
> +    if (env->priv == PRV_U) {
> +        /*
> +         * One corner case is when sctrclr is executed from VU-mode and
> +         * mstateen.CTR = 0, in which case we are supposed to raise
> +         * RISCV_EXCP_ILLEGAL_INST. This case is already handled in
> +         * smstateen_acc_ok().
> +         */
> +        uint32_t excep = env->virt_enabled ? 
> RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
> +            RISCV_EXCP_ILLEGAL_INST;
> +        riscv_raise_exception(env, excep, GETPC());
> +    }
> +
> +    riscv_ctr_clear(env);
> +}
> +
>  void helper_wfi(CPURISCVState *env)
>  {
>      CPUState *cs = env_cpu(env);
>
> --
> 2.34.1
>
>