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[PULL 31/32] target/riscv: Apply modularized matching conditions for wat
From: |
Alistair Francis |
Subject: |
[PULL 31/32] target/riscv: Apply modularized matching conditions for watchpoint |
Date: |
Thu, 27 Jun 2024 20:00:52 +1000 |
From: Alvin Chang <alvinga@andestech.com>
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the watchpoints.
This commit also changes the behavior of looping the triggers. In
previous implementation, if we have a type 2 trigger and
env->virt_enabled is true, we directly return false to stop the loop.
Now we keep looping all the triggers until we find a matched trigger.
Only load/store bits and loaded/stored address should be further checked
in riscv_cpu_debug_check_watchpoint().
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240626132247.2761286-3-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.c | 26 ++++++--------------------
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 11125f333b..c290d6002e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -901,13 +901,12 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
for (i = 0; i < RV_MAX_TRIGGERS; i++) {
trigger_type = get_trigger_type(env, i);
+ if (!trigger_common_match(env, trigger_type, i)) {
+ continue;
+ }
+
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
- /* type 2 trigger cannot be fired in VU/VS mode */
- if (env->virt_enabled) {
- return false;
- }
-
ctrl = env->tdata1[i];
addr = env->tdata2[i];
flags = 0;
@@ -920,10 +919,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
}
if ((wp->flags & flags) && (wp->vaddr == addr)) {
- /* check U/S/M bit against current privilege level */
- if ((ctrl >> 3) & BIT(env->priv)) {
- return true;
- }
+ return true;
}
break;
case TRIGGER_TYPE_AD_MATCH6:
@@ -939,17 +935,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
}
if ((wp->flags & flags) && (wp->vaddr == addr)) {
- if (env->virt_enabled) {
- /* check VU/VS bit against current privilege level */
- if ((ctrl >> 23) & BIT(env->priv)) {
- return true;
- }
- } else {
- /* check U/S/M bit against current privilege level */
- if ((ctrl >> 3) & BIT(env->priv)) {
- return true;
- }
- }
+ return true;
}
break;
default:
--
2.45.2
- [PULL 20/32] target/riscv: Support the version for ss1p13, (continued)
- [PULL 20/32] target/riscv: Support the version for ss1p13, Alistair Francis, 2024/06/27
- [PULL 21/32] hw/riscv/virt.c: Make block devices default to virtio, Alistair Francis, 2024/06/27
- [PULL 22/32] target/riscv: Fix froundnx.h nanbox check, Alistair Francis, 2024/06/27
- [PULL 23/32] target/riscv: fix instructions count handling in icount mode, Alistair Francis, 2024/06/27
- [PULL 27/32] target/riscv: Add multi extension implied rules, Alistair Francis, 2024/06/27
- [PULL 25/32] target/riscv: Introduce extension implied rule helpers, Alistair Francis, 2024/06/27
- [PULL 26/32] target/riscv: Add MISA extension implied rules, Alistair Francis, 2024/06/27
- [PULL 24/32] target/riscv: Introduce extension implied rules definition, Alistair Francis, 2024/06/27
- [PULL 28/32] target/riscv: Add Zc extension implied rule, Alistair Francis, 2024/06/27
- [PULL 29/32] target/riscv: Remove extension auto-update check statements, Alistair Francis, 2024/06/27
- [PULL 31/32] target/riscv: Apply modularized matching conditions for watchpoint,
Alistair Francis <=
- [PULL 30/32] target/riscv: Add functions for common matching conditions of trigger, Alistair Francis, 2024/06/27
- [PULL 32/32] target/riscv: Apply modularized matching conditions for icount trigger, Alistair Francis, 2024/06/27
- Re: [PULL 00/32] riscv-to-apply queue, Richard Henderson, 2024/06/27