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[PULL 02/32] target/riscv: Move Guest irqs out of the core local irqs ra
From: |
Alistair Francis |
Subject: |
[PULL 02/32] target/riscv: Move Guest irqs out of the core local irqs range. |
Date: |
Thu, 27 Jun 2024 20:00:23 +1000 |
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
Qemu maps IRQs 0:15 for core interrupts and 16 onward for
guest interrupts which are later translated to hgiep in
`riscv_cpu_set_irq()` function.
With virtual IRQ support added, software now can fully
use the whole local interrupt range without any actual
hardware attached.
This change moves the guest interrupt range after the
core local interrupt range to avoid clash.
Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ
filtering support.")
Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ
filtering support.")
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240520125157.311503-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 ++-
target/riscv/csr.c | 9 ++++++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 74318a925c..a470fda9be 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -695,7 +695,8 @@ typedef enum RISCVException {
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_PMU_OVF 13
-#define IRQ_LOCAL_MAX 16
+#define IRQ_LOCAL_MAX 64
+/* -1 is due to bit zero of hgeip and hgeie being ROZ. */
#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
/* mip masks */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index dd89edb06a..ee33019b03 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1145,7 +1145,14 @@ static RISCVException write_stimecmph(CPURISCVState
*env, int csrno,
#define VSTOPI_NUM_SRCS 5
-#define LOCAL_INTERRUPTS (~0x1FFF)
+/*
+ * All core local interrupts except the fixed ones 0:12. This macro is for
+ * virtual interrupts logic so please don't change this to avoid messing up
+ * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and
+ * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for
+ * VS level`.
+ */
+#define LOCAL_INTERRUPTS (~0x1FFFULL)
static const uint64_t delegable_ints =
S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
--
2.45.2
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2024/06/27
- [PULL 01/32] target/riscv: Extend virtual irq csrs masks to be 64 bit wide., Alistair Francis, 2024/06/27
- [PULL 02/32] target/riscv: Move Guest irqs out of the core local irqs range.,
Alistair Francis <=
- [PULL 03/32] target/riscv: zvbb implies zvkb, Alistair Francis, 2024/06/27
- [PULL 05/32] hw/riscv/virt.c: add aplic nodename helper, Alistair Francis, 2024/06/27
- [PULL 04/32] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic(), Alistair Francis, 2024/06/27
- [PULL 07/32] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 08/32] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation', Alistair Francis, 2024/06/27
- [PULL 06/32] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 09/32] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 11/32] hw/riscv/virt.c: imsics DT: add '#msi-cells', Alistair Francis, 2024/06/27
- [PULL 13/32] target/riscv/kvm: handle the exit with debug reason, Alistair Francis, 2024/06/27