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[PULL 12/18] hw/arm/virt: Add serial aliases in DTB
From: |
Peter Maydell |
Subject: |
[PULL 12/18] hw/arm/virt: Add serial aliases in DTB |
Date: |
Sat, 22 Jun 2024 13:06:37 +0100 |
If there is more than one UART in the DTB, then there is no guarantee
on which order a guest is supposed to initialise them. The standard
solution to this is "serialN" entries in the "/aliases" node of the
dtb which give the nodename of the UARTs.
At the moment we only have two UARTs in the DTB when one is for
the Secure world and one for the Non-Secure world, so this isn't
really a problem. However if we want to add a second NS UART we'll
need the aliases to ensure guests pick the right one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240610162343.2131524-2-peter.maydell@linaro.org
---
hw/arm/virt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index c7a1f754e72..61a9d47c026 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -284,6 +284,8 @@ static void create_fdt(VirtMachineState *vms)
}
}
+ qemu_fdt_add_subnode(fdt, "/aliases");
+
/* Clock node, for the benefit of the UART. The kernel device tree
* binding documentation claims the PL011 node clock properties are
* optional but in practice if you omit them the kernel refuses to
@@ -939,7 +941,9 @@ static void create_uart(const VirtMachineState *vms, int
uart,
if (uart == VIRT_UART) {
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
+ qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
} else {
+ qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
/* Mark as not usable by the normal world */
qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
--
2.34.1
- [PULL 00/18] target-arm queue, Peter Maydell, 2024/06/22
- [PULL 01/18] hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue, Peter Maydell, 2024/06/22
- [PULL 07/18] scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to the crypto component, Peter Maydell, 2024/06/22
- [PULL 03/18] hw/intc/arm_gic: Fix deactivation of SPI lines, Peter Maydell, 2024/06/22
- [PULL 04/18] hw/arm/xilinx_zynq: Fix IRQ/FIQ routing, Peter Maydell, 2024/06/22
- [PULL 06/18] scripts/coverity-scan/COMPONENTS.md: Fix 'char' component, Peter Maydell, 2024/06/22
- [PULL 12/18] hw/arm/virt: Add serial aliases in DTB,
Peter Maydell <=
- [PULL 16/18] hw/misc: Set valid access size for Exynos4210 RNG, Peter Maydell, 2024/06/22
- [PULL 05/18] scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI, Peter Maydell, 2024/06/22
- [PULL 02/18] hw/arm/sbsa-ref: switch to 1GHz timer frequency, Peter Maydell, 2024/06/22
- [PULL 08/18] scripts/coverity-scan/COMPONENTS.md: Fix monitor component, Peter Maydell, 2024/06/22
- [PULL 09/18] scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs, Peter Maydell, 2024/06/22
- [PULL 11/18] hw/usb/hcd-dwc2: Handle invalid address access in read and write functions, Peter Maydell, 2024/06/22
- [PULL 14/18] hw/arm/virt: allow creation of a second NonSecure UART, Peter Maydell, 2024/06/22
- [PULL 15/18] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs, Peter Maydell, 2024/06/22
- [PULL 18/18] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine, Peter Maydell, 2024/06/22
- [PULL 10/18] hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu, Peter Maydell, 2024/06/22