Re: [PATCH v3 1/3] hw/misc/zynq_slcr: Add boot-mode property

[Francisco Iglesias]

On Thu, Jun 20, 2024 at 04:11:37PM +0530, Sai Pavan Boddu wrote:
> boot-mode property sets user values into BOOT_MODE register, on hardware
> these are derived from board switches.
> 
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>

Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>

> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
> ---
>  hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index 3412ff099ea..ad814c3a79b 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -24,6 +24,8 @@
>  #include "hw/registerfields.h"
>  #include "hw/qdev-clock.h"
>  #include "qom/object.h"
> +#include "hw/qdev-properties.h"
> +#include "qapi/error.h"
>  
>  #ifndef ZYNQ_SLCR_ERR_DEBUG
>  #define ZYNQ_SLCR_ERR_DEBUG 0
> @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250)
>  
>  REG32(REBOOT_STATUS, 0x258)
>  REG32(BOOT_MODE, 0x25c)
> +    FIELD(BOOT_MODE, BOOT_MODE, 0, 4)
>  
>  REG32(APU_CTRL, 0x300)
>  REG32(WDT_CLK_SEL, 0x304)
> @@ -195,6 +198,7 @@ struct ZynqSLCRState {
>      Clock *ps_clk;
>      Clock *uart0_ref_clk;
>      Clock *uart1_ref_clk;
> +    uint8_t boot_mode;
>  };
>  
>  /*
> @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType 
> type)
>      s->regs[R_FPGA_RST_CTRL]  = 0x01F33F0F;
>      s->regs[R_RST_REASON]     = 0x00000040;
>  
> -    s->regs[R_BOOT_MODE]      = 0x00000001;
> +    s->regs[R_BOOT_MODE]      = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK;
>  
>      /* 0x700 - 0x7D4 */
>      for (i = 0; i < 54; i++) {
> @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks = {
>      QDEV_CLOCK_END
>  };
>  
> +static void zynq_slcr_realize(DeviceState *dev, Error **errp)
> +{
> +    ZynqSLCRState *s = ZYNQ_SLCR(dev);
> +
> +    if (s->boot_mode > 0xF) {
> +        error_setg(errp, "Invalid boot mode %d specified", s->boot_mode);
> +    }
> +}
> +
>  static void zynq_slcr_init(Object *obj)
>  {
>      ZynqSLCRState *s = ZYNQ_SLCR(obj);
> @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr = {
>      }
>  };
>  
> +static Property zynq_slcr_props[] = {
> +    DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
>  static void zynq_slcr_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
>      ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>      dc->vmsd = &vmstate_zynq_slcr;
> +    dc->realize = zynq_slcr_realize;
>      rc->phases.enter = zynq_slcr_reset_init;
>      rc->phases.hold  = zynq_slcr_reset_hold;
>      rc->phases.exit  = zynq_slcr_reset_exit;
> +    device_class_set_props(dc, zynq_slcr_props);
>  }
>  
>  static const TypeInfo zynq_slcr_info = {
> -- 
> 2.34.1
>