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[Stable-8.2.5 25/45] hw/intc/arm_gic: Fix handling of NS view of GICC_AP
From: |
Michael Tokarev |
Subject: |
[Stable-8.2.5 25/45] hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n> |
Date: |
Fri, 7 Jun 2024 22:12:44 +0300 |
From: Andrey Shumilin <shum.sdl@nppct.ru>
In gic_cpu_read() and gic_cpu_write(), we delegate the handling of
reading and writing the Non-Secure view of the GICC_APR<n> registers
to functions gic_apr_ns_view() and gic_apr_write_ns_view().
Unfortunately we got the order of the arguments wrong, swapping the
CPU number and the register number (which the compiler doesn't catch
because they're both integers).
Most guests probably didn't notice this bug because directly
accessing the APR registers is typically something only done by
firmware when it is doing state save for going into a sleep mode.
Correct the mismatched call arguments.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: 51fd06e0ee ("hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n>
registers")
Signed-off-by: Andrey Shumilin <shum.sdl@nppct.ru>
[PMM: Rewrote commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée<alex.bennee@linaro.org>
(cherry picked from commit daafa78b297291fea36fb4daeed526705fa7c035)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 074cf50af2..e4b8437f8b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1658,7 +1658,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int
offset,
*data = s->h_apr[gic_get_vcpu_real_id(cpu)];
} else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
- *data = gic_apr_ns_view(s, regno, cpu);
+ *data = gic_apr_ns_view(s, cpu, regno);
} else {
*data = s->apr[regno][cpu];
}
@@ -1746,7 +1746,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu,
int offset,
s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
} else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
- gic_apr_write_ns_view(s, regno, cpu, value);
+ gic_apr_write_ns_view(s, cpu, regno, value);
} else {
s->apr[regno][cpu] = value;
}
--
2.39.2
- [Stable-8.2.5 00/45] Patch Round-up for stable 8.2.5, frozen on 2024-06-07, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 20/45] gitlab: Update msys2-64bit runner tags, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 22/45] gitlab: use $MAKE instead of 'make', Michael Tokarev, 2024/06/07
- [Stable-8.2.5 23/45] gitlab: use 'setarch -R' to workaround tsan bug, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 24/45] hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 25/45] hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>,
Michael Tokarev <=
- [Stable-8.2.5 26/45] target/arm: Disable SVE extensions when SVE is disabled, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 29/45] hw/intc/riscv_aplic: APLICs should add child earlier than realize, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 30/45] target/riscv/kvm: tolerate KVM disable ext errors, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 27/45] qio: Inherit follow_coroutine_ctx across TLS, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 28/45] iotests: test NBD+TLS+iothread, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 31/45] target/riscv: Fix the element agnostic function problem, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 32/45] target/riscv/cpu.c: fix Zvkb extension config, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 33/45] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 34/45] target/riscv: rvv: Check single width operator for vector fp widen instructions, Michael Tokarev, 2024/06/07
- [Stable-8.2.5 35/45] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Michael Tokarev, 2024/06/07