Re: [PATCH v2 0/2] target/riscv: Minor fixes and improvements for Virtual IRQs

[Alistair Francis]

On Mon, May 20, 2024 at 10:52 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> This series contains few miscellaneous fixes related to Virtual IRQs
> and related code. The first patch changes CSR mask widths to 64bit
> as AIA introduces half CSRs in case of 32bit systems.
>
> Second patch fixes guest and core local IRQ overlap. Qemu creates
> a single IRQ range which is shared between core local interrupts
> and guests in riscv_cpu_init(). Even though, in the current state
> there is no device generating interrupts in the 13:63 range, and
> virtual IRQ logic in Qemu also doesn't go through riscv_cpu_set_irq()
> path, it's better to keep local and guest range separate to avoid
> confusion and any future issues.
>
> Patches can be found here on github [0] and v1 of the series
> can be found here [1].
>
> Patches are based on alistair/riscv-to-apply.next.
>
> [0] https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/irq_fixes_v2
> [1] https://lore.kernel.org/all/20240513114602.72098-1-rkanwal@rivosinc.com/
>
> Changes from v1->v2:
> 1. Check patch fixes.
> 2. Removed commit title split from Fixes tags.
>
> Rajnesh Kanwal (2):
>   target/riscv: Extend virtual irq csrs masks to be 64 bit wide.
>   target/riscv: Move Guest irqs out of the core local irqs range.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu_bits.h |  3 ++-
>  target/riscv/csr.c      | 23 +++++++++++++++--------
>  2 files changed, 17 insertions(+), 9 deletions(-)
>
> --
> 2.34.1
>
>