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[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
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From: |
Alistair Francis |
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Subject: |
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs |
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Date: |
Tue, 28 May 2024 12:43:27 +1000 |
From: Alistair Francis <alistair23@gmail.com>
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index e236c8b5b7..297cfa2f63 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2190,7 +2190,22 @@ static const char *csr_name(int csrno)
case 0x0383: return "mibound";
case 0x0384: return "mdbase";
case 0x0385: return "mdbound";
- case 0x03a0: return "pmpcfg3";
+ case 0x03a0: return "pmpcfg0";
+ case 0x03a1: return "pmpcfg1";
+ case 0x03a2: return "pmpcfg2";
+ case 0x03a3: return "pmpcfg3";
+ case 0x03a4: return "pmpcfg4";
+ case 0x03a5: return "pmpcfg5";
+ case 0x03a6: return "pmpcfg6";
+ case 0x03a7: return "pmpcfg7";
+ case 0x03a8: return "pmpcfg8";
+ case 0x03a9: return "pmpcfg9";
+ case 0x03aa: return "pmpcfg10";
+ case 0x03ab: return "pmpcfg11";
+ case 0x03ac: return "pmpcfg12";
+ case 0x03ad: return "pmpcfg13";
+ case 0x03ae: return "pmpcfg14";
+ case 0x03af: return "pmpcfg15";
case 0x03b0: return "pmpaddr0";
case 0x03b1: return "pmpaddr1";
case 0x03b2: return "pmpaddr2";
@@ -2207,6 +2222,54 @@ static const char *csr_name(int csrno)
case 0x03bd: return "pmpaddr13";
case 0x03be: return "pmpaddr14";
case 0x03bf: return "pmpaddr15";
+ case 0x03c0: return "pmpaddr16";
+ case 0x03c1: return "pmpaddr17";
+ case 0x03c2: return "pmpaddr18";
+ case 0x03c3: return "pmpaddr19";
+ case 0x03c4: return "pmpaddr20";
+ case 0x03c5: return "pmpaddr21";
+ case 0x03c6: return "pmpaddr22";
+ case 0x03c7: return "pmpaddr23";
+ case 0x03c8: return "pmpaddr24";
+ case 0x03c9: return "pmpaddr25";
+ case 0x03ca: return "pmpaddr26";
+ case 0x03cb: return "pmpaddr27";
+ case 0x03cc: return "pmpaddr28";
+ case 0x03cd: return "pmpaddr29";
+ case 0x03ce: return "pmpaddr30";
+ case 0x03cf: return "pmpaddr31";
+ case 0x03d0: return "pmpaddr32";
+ case 0x03d1: return "pmpaddr33";
+ case 0x03d2: return "pmpaddr34";
+ case 0x03d3: return "pmpaddr35";
+ case 0x03d4: return "pmpaddr36";
+ case 0x03d5: return "pmpaddr37";
+ case 0x03d6: return "pmpaddr38";
+ case 0x03d7: return "pmpaddr39";
+ case 0x03d8: return "pmpaddr40";
+ case 0x03d9: return "pmpaddr41";
+ case 0x03da: return "pmpaddr42";
+ case 0x03db: return "pmpaddr43";
+ case 0x03dc: return "pmpaddr44";
+ case 0x03dd: return "pmpaddr45";
+ case 0x03de: return "pmpaddr46";
+ case 0x03df: return "pmpaddr47";
+ case 0x03e0: return "pmpaddr48";
+ case 0x03e1: return "pmpaddr49";
+ case 0x03e2: return "pmpaddr50";
+ case 0x03e3: return "pmpaddr51";
+ case 0x03e4: return "pmpaddr52";
+ case 0x03e5: return "pmpaddr53";
+ case 0x03e6: return "pmpaddr54";
+ case 0x03e7: return "pmpaddr55";
+ case 0x03e8: return "pmpaddr56";
+ case 0x03e9: return "pmpaddr57";
+ case 0x03ea: return "pmpaddr58";
+ case 0x03eb: return "pmpaddr59";
+ case 0x03ec: return "pmpaddr60";
+ case 0x03ed: return "pmpaddr61";
+ case 0x03ee: return "pmpaddr62";
+ case 0x03ef: return "pmpaddr63";
case 0x0780: return "mtohost";
case 0x0781: return "mfromhost";
case 0x0782: return "mreset";
--
2.45.1
- [PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions, (continued)
- [PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions, Alistair Francis, 2024/05/27
- [PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Alistair Francis, 2024/05/27
- [PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception(), Alistair Francis, 2024/05/27
- [PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults, Alistair Francis, 2024/05/27
- [PULL 23/28] target/riscv: Remove experimental prefix from "B" extension, Alistair Francis, 2024/05/27
- [PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature(), Alistair Francis, 2024/05/27
- [PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA, Alistair Francis, 2024/05/27
- [PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Alistair Francis, 2024/05/27
- [PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation, Alistair Francis, 2024/05/27
- [PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR, Alistair Francis, 2024/05/27
- [PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs,
Alistair Francis <=
- Re: [PULL 00/28] riscv-to-apply queue, Richard Henderson, 2024/05/28