[PATCH v2 36/37] target/sparc: Implement monitor ASIs

[Richard Henderson]

Ignore the "monitor" portion and treat them the same
as their base ASIs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/asi.h         | 4 ++++
 target/sparc/ldst_helper.c | 4 ++++
 target/sparc/translate.c   | 8 ++++++++
 3 files changed, 16 insertions(+)

diff --git a/target/sparc/asi.h b/target/sparc/asi.h
index a66829674b..14ffaa3842 100644
--- a/target/sparc/asi.h
+++ b/target/sparc/asi.h
@@ -144,6 +144,8 @@
  * ASIs, "(4V)" designates SUN4V specific ASIs.  "(NG4)" designates SPARC-T4
  * and later ASIs.
  */
+#define ASI_MON_AIUP            0x12 /* (VIS4) Primary, user, monitor   */
+#define ASI_MON_AIUS            0x13 /* (VIS4) Secondary, user, monitor */
 #define ASI_REAL                0x14 /* Real address, cacheable          */
 #define ASI_PHYS_USE_EC                0x14 /* PADDR, E-cacheable              
*/
 #define ASI_REAL_IO             0x15 /* Real address, non-cacheable      */
@@ -257,6 +259,8 @@
 #define ASI_UDBL_CONTROL_R     0x7f /* External UDB control regs rd low*/
 #define ASI_INTR_R             0x7f /* IRQ vector dispatch read        */
 #define ASI_INTR_DATAN_R       0x7f /* (III) In irq vector data reg N  */
+#define ASI_MON_P               0x84 /* (VIS4) Primary, monitor         */
+#define ASI_MON_S               0x85 /* (VIS4) Secondary, monitor       */
 #define ASI_PIC                        0xb0 /* (NG4) PIC registers             
*/
 #define ASI_PST8_P             0xc0 /* Primary, 8 8-bit, partial       */
 #define ASI_PST8_S             0xc1 /* Secondary, 8 8-bit, partial     */
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 7bdf99e0c0..2d48e98bf4 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1395,6 +1395,10 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong 
addr,
     case ASI_TWINX_PL: /* Primary, twinx, LE */
     case ASI_TWINX_S:  /* Secondary, twinx */
     case ASI_TWINX_SL: /* Secondary, twinx, LE */
+    case ASI_MON_P:
+    case ASI_MON_S:
+    case ASI_MON_AIUP:
+    case ASI_MON_AIUS:
         /* These are always handled inline.  */
         g_assert_not_reached();
 
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index dba0eaa30c..d2478a0246 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1607,6 +1607,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, 
MemOp memop)
         case ASI_BLK_AIUP_L_4V:
         case ASI_BLK_AIUP:
         case ASI_BLK_AIUPL:
+        case ASI_MON_AIUP:
             mem_idx = MMU_USER_IDX;
             break;
         case ASI_AIUS:  /* As if user secondary */
@@ -1617,6 +1618,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, 
MemOp memop)
         case ASI_BLK_AIUS_L_4V:
         case ASI_BLK_AIUS:
         case ASI_BLK_AIUSL:
+        case ASI_MON_AIUS:
             mem_idx = MMU_USER_SECONDARY_IDX;
             break;
         case ASI_S:  /* Secondary */
@@ -1630,6 +1632,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, 
MemOp memop)
         case ASI_FL8_SL:
         case ASI_FL16_S:
         case ASI_FL16_SL:
+        case ASI_MON_S:
             if (mem_idx == MMU_USER_IDX) {
                 mem_idx = MMU_USER_SECONDARY_IDX;
             } else if (mem_idx == MMU_KERNEL_IDX) {
@@ -1647,6 +1650,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, 
MemOp memop)
         case ASI_FL8_PL:
         case ASI_FL16_P:
         case ASI_FL16_PL:
+        case ASI_MON_P:
             break;
         }
         switch (asi) {
@@ -1664,6 +1668,10 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, 
MemOp memop)
         case ASI_SL:
         case ASI_P:
         case ASI_PL:
+        case ASI_MON_P:
+        case ASI_MON_S:
+        case ASI_MON_AIUP:
+        case ASI_MON_AIUS:
             type = GET_ASI_DIRECT;
             break;
         case ASI_TWINX_REAL:
-- 
2.34.1