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[PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the devi
From: |
CLEMENT MATHIEU--DRIF |
Subject: |
[PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the device |
Date: |
Wed, 15 May 2024 07:14:17 +0000 |
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
hw/pci/pci.c | 24 ++++++++++++++----------
include/hw/pci/pci_device.h | 1 +
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 045d69f4c1..e5f72f9f1d 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -116,6 +116,12 @@ static GSequence *pci_acpi_index_list(void)
return used_acpi_index_list;
}
+static void pci_set_master(PCIDevice *d, bool enable)
+{
+ memory_region_set_enabled(&d->bus_master_enable_region, enable);
+ d->is_master = enable; /* cache the status */
+}
+
static void pci_init_bus_master(PCIDevice *pci_dev)
{
AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
@@ -123,7 +129,7 @@ static void pci_init_bus_master(PCIDevice *pci_dev)
memory_region_init_alias(&pci_dev->bus_master_enable_region,
OBJECT(pci_dev), "bus master",
dma_as->root, 0,
memory_region_size(dma_as->root));
- memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
+ pci_set_master(pci_dev, false);
memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
&pci_dev->bus_master_enable_region);
}
@@ -657,9 +663,8 @@ static int get_pci_config_device(QEMUFile *f, void *pv,
size_t size,
pci_bridge_update_mappings(PCI_BRIDGE(s));
}
- memory_region_set_enabled(&s->bus_master_enable_region,
- pci_get_word(s->config + PCI_COMMAND)
- & PCI_COMMAND_MASTER);
+ pci_set_master(s,
+ pci_get_word(s->config + PCI_COMMAND) & PCI_COMMAND_MASTER);
g_free(config);
return 0;
@@ -1611,9 +1616,9 @@ void pci_default_write_config(PCIDevice *d, uint32_t
addr, uint32_t val_in, int
if (ranges_overlap(addr, l, PCI_COMMAND, 2)) {
pci_update_irq_disabled(d, was_irq_disabled);
- memory_region_set_enabled(&d->bus_master_enable_region,
- (pci_get_word(d->config + PCI_COMMAND)
- & PCI_COMMAND_MASTER) && d->has_power);
+ pci_set_master(d,
+ (pci_get_word(d->config + PCI_COMMAND) &
+ PCI_COMMAND_MASTER) && d->has_power);
}
msi_write_config(d, addr, val_in, l);
@@ -2888,9 +2893,8 @@ void pci_set_power(PCIDevice *d, bool state)
d->has_power = state;
pci_update_mappings(d);
- memory_region_set_enabled(&d->bus_master_enable_region,
- (pci_get_word(d->config + PCI_COMMAND)
- & PCI_COMMAND_MASTER) && d->has_power);
+ pci_set_master(d, (pci_get_word(d->config + PCI_COMMAND)
+ & PCI_COMMAND_MASTER) && d->has_power);
if (!d->has_power) {
pci_device_reset(d);
}
diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h
index d3dd0f64b2..7fa501569a 100644
--- a/include/hw/pci/pci_device.h
+++ b/include/hw/pci/pci_device.h
@@ -87,6 +87,7 @@ struct PCIDevice {
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
+ bool is_master;
MemoryRegion bus_master_container_region;
MemoryRegion bus_master_enable_region;
--
2.44.0
- [PATCH ats_vtd v2 02/25] intel_iommu: make types match, (continued)
- [PATCH ats_vtd v2 02/25] intel_iommu: make types match, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 09/25] pcie: add helper to declare PASID capability for a pcie device, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 15/25] pci: add IOMMU operations to get address spaces and memory regions with PASID, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 03/25] intel_iommu: check if the input address is canonical, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 04/25] intel_iommu: set accessed and dirty bits during first stage translation, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 08/25] memory: add permissions in IOMMUAccessFlags, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 05/25] intel_iommu: return page walk level even when the translation fails, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 12/25] intel_iommu: add an internal API to find an address space with PASID, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 10/25] pcie: helper functions to check if PASID and ATS are enabled, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 06/25] intel_iommu: extract device IOTLB invalidation logic, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the device,
CLEMENT MATHIEU--DRIF <=
- [PATCH ats_vtd v2 11/25] intel_iommu: declare supported PASID size, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 13/25] intel_iommu: add support for PASID-based device IOTLB invalidation, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 17/25] intel_iommu: implement the get_address_space_pasid iommu operation, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 18/25] intel_iommu: implement the get_memory_region_pasid iommu operation, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 16/25] pci: add a pci-level initialization function for iommu notifiers, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 22/25] memory: add an API for ATS support, CLEMENT MATHIEU--DRIF, 2024/05/15
- [PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry, CLEMENT MATHIEU--DRIF, 2024/05/15