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[PULL 30/36] hw/arm: Add GMAC devices to NPCM7XX SoC
From: |
Peter Maydell |
Subject: |
[PULL 30/36] hw/arm: Add GMAC devices to NPCM7XX SoC |
Date: |
Fri, 2 Feb 2024 15:36:31 +0000 |
From: Hao Wu <wuhaotsh@google.com>
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-3-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm7xx.h | 2 ++
hw/arm/npcm7xx.c | 37 +++++++++++++++++++++++++++++++++++--
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 72c77220964..4e0d2101885 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -29,6 +29,7 @@
#include "hw/misc/npcm7xx_pwm.h"
#include "hw/misc/npcm7xx_rng.h"
#include "hw/net/npcm7xx_emc.h"
+#include "hw/net/npcm_gmac.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
@@ -104,6 +105,7 @@ struct NPCM7xxState {
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
+ NPCMGMACState gmac[2];
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi[2];
};
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index e3243a520d8..d9dfdfcd51a 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -84,8 +84,10 @@ enum NPCM7xxInterrupt {
NPCM7XX_UART1_IRQ,
NPCM7XX_UART2_IRQ,
NPCM7XX_UART3_IRQ,
+ NPCM7XX_GMAC1_IRQ = 14,
NPCM7XX_EMC1RX_IRQ = 15,
NPCM7XX_EMC1TX_IRQ,
+ NPCM7XX_GMAC2_IRQ,
NPCM7XX_MMC_IRQ = 26,
NPCM7XX_PSPI2_IRQ = 28,
NPCM7XX_PSPI1_IRQ = 31,
@@ -229,6 +231,12 @@ static const hwaddr npcm7xx_pspi_addr[] = {
0xf0201000,
};
+/* Register base address for each GMAC Module */
+static const hwaddr npcm7xx_gmac_addr[] = {
+ 0xf0802000,
+ 0xf0804000,
+};
+
static const struct {
hwaddr regs_addr;
uint32_t unconnected_pins;
@@ -457,6 +465,10 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
}
+ for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
+ object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC);
+ }
+
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
}
@@ -688,6 +700,29 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
}
+ /*
+ * GMAC Modules. Cannot fail.
+ */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) != ARRAY_SIZE(s->gmac));
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) != 2);
+ for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
+
+ /*
+ * The device exists regardless of whether it's connected to a QEMU
+ * netdev backend. So always instantiate it even if there is no
+ * backend.
+ */
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]);
+ int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ;
+ /*
+ * N.B. The values for the second argument sysbus_connect_irq are
+ * chosen to match the registration order in npcm7xx_emc_realize.
+ */
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+ }
+
/*
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
* specified, but this is a programming error.
@@ -750,8 +785,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
- create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
- create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
--
2.34.1
- [PULL 18/36] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[], (continued)
- [PULL 18/36] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[], Peter Maydell, 2024/02/02
- [PULL 17/36] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[], Peter Maydell, 2024/02/02
- [PULL 12/36] doc/sphinx/hxtool.py: add optional label argument to SRST directive, Peter Maydell, 2024/02/02
- [PULL 19/36] hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[], Peter Maydell, 2024/02/02
- [PULL 22/36] pci-host: designware: Limit value range of iATU viewport register, Peter Maydell, 2024/02/02
- [PULL 24/36] hw/arm/z2: convert DPRINTF to trace events and guest errors, Peter Maydell, 2024/02/02
- [PULL 26/36] hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints, Peter Maydell, 2024/02/02
- [PULL 27/36] hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints, Peter Maydell, 2024/02/02
- [PULL 21/36] hw/arm/zynq: Check for CPU types in machine_run_board_init(), Peter Maydell, 2024/02/02
- [PULL 28/36] hw/xen: convert stderr prints to error/warn reports, Peter Maydell, 2024/02/02
- [PULL 30/36] hw/arm: Add GMAC devices to NPCM7XX SoC,
Peter Maydell <=
- [PULL 32/36] hw/net: GMAC Rx Implementation, Peter Maydell, 2024/02/02
- [PULL 29/36] hw/net: Add NPCMXXX GMAC device, Peter Maydell, 2024/02/02
- [PULL 31/36] tests/qtest: Creating qtest for GMAC Module, Peter Maydell, 2024/02/02
- [PULL 23/36] hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors, Peter Maydell, 2024/02/02
- [PULL 25/36] hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports, Peter Maydell, 2024/02/02
- [PULL 33/36] hw/net: GMAC Tx Implementation, Peter Maydell, 2024/02/02
- [PULL 36/36] hw/arm: Connect SPI Controller to BCM2835, Peter Maydell, 2024/02/02
- [PULL 35/36] hw/ssi: Implement BCM2835 SPI Controller, Peter Maydell, 2024/02/02
- [PULL 34/36] tests/qtest: Adding PCS Module test to GMAC Qtest, Peter Maydell, 2024/02/02
- Re: [PULL 00/36] target-arm queue, Peter Maydell, 2024/02/03