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[PULL 00/57] tcg patch queue
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From: |
Richard Henderson |
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Subject: |
[PULL 00/57] tcg patch queue |
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Date: |
Fri, 2 Feb 2024 15:49:38 +1000 |
The following changes since commit 14639717bf379480e937716fcaf1e72b47fd4c5f:
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into
staging (2024-01-31 19:53:45 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240202
for you to fetch changes up to 73e095fc71dfeb8f5f767d9ac71078e562d935b0:
target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK (2024-02-02 14:40:06
+1000)
----------------------------------------------------------------
tests/tcg: Fix multiarch/gdbstub/prot-none.py
hw/core: Convert cpu_mmu_index to a CPUClass hook
tcg/loongarch64: Set vector registers call clobbered
target/sparc: floating-point cleanup
----------------------------------------------------------------
Ilya Leoshkevich (1):
tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test
Richard Henderson (56):
include/hw/core: Add mmu_index to CPUClass
target/alpha: Split out alpha_env_mmu_index
target/alpha: Populate CPUClass.mmu_index
target/arm: Split out arm_env_mmu_index
target/arm: Populate CPUClass.mmu_index
target/avr: Populate CPUClass.mmu_index
target/cris: Cache mem_index in DisasContext
target/cris: Populate CPUClass.mmu_index
target/hppa: Populate CPUClass.mmu_index
target/i386: Populate CPUClass.mmu_index
target/loongarch: Populate CPUClass.mmu_index
target/loongarch: Rename MMU_IDX_*
target/m68k: Populate CPUClass.mmu_index
target/microblaze: Populate CPUClass.mmu_index
target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill
target/mips: Split out mips_env_mmu_index
target/mips: Populate CPUClass.mmu_index
target/nios2: Populate CPUClass.mmu_index
target/openrisc: Populate CPUClass.mmu_index
target/ppc: Split out ppc_env_mmu_index
target/ppc: Populate CPUClass.mmu_index
target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
target/riscv: Populate CPUClass.mmu_index
target/rx: Populate CPUClass.mmu_index
target/s390x: Split out s390x_env_mmu_index
target/s390x: Populate CPUClass.mmu_index
target/sh4: Populate CPUClass.mmu_index
target/sparc: Populate CPUClass.mmu_index
target/tricore: Populate CPUClass.mmu_index
target/xtensa: Populate CPUClass.mmu_index
include/exec: Implement cpu_mmu_index generically
include/exec: Change cpu_mmu_index argument to CPUState
tcg/loongarch64: Set vector registers call clobbered
target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY
target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL
target/sparc: Remove gen_dest_fpr_F
target/sparc: Introduce gen_{load,store}_fpr_Q
target/sparc: Inline FNEG, FABS
target/sparc: Use i128 for FSQRTq
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
target/sparc: Use i128 for FqTOs, FqTOi
target/sparc: Use i128 for FqTOd, FqTOx
target/sparc: Use i128 for FCMPq, FCMPEq
target/sparc: Use i128 for FsTOq, FiTOq
target/sparc: Use i128 for FdTOq, FxTOq
target/sparc: Use i128 for Fdmulq
target/sparc: Remove qt0, qt1 temporaries
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
target/sparc: Split ver from env->fsr
target/sparc: Clear cexc and ftt in do_check_ieee_exceptions
target/sparc: Merge check_ieee_exceptions with FPop helpers
target/sparc: Split cexc and ftt from env->fsr
target/sparc: Remove cpu_fsr
target/sparc: Split fcc out of env->fsr
target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK
include/exec/cpu-all.h | 4 +
include/exec/cpu-common.h | 21 +
include/hw/core/cpu.h | 3 +
target/alpha/cpu.h | 2 +-
target/arm/cpu.h | 13 -
target/arm/internals.h | 5 +
target/avr/cpu.h | 7 -
target/cris/cpu.h | 4 -
target/hexagon/cpu.h | 9 -
target/hppa/cpu.h | 13 -
target/i386/cpu.h | 7 -
target/loongarch/cpu.h | 18 +-
target/m68k/cpu.h | 4 -
target/microblaze/cpu.h | 15 -
target/mips/cpu.h | 6 +-
target/nios2/cpu.h | 6 -
target/openrisc/cpu.h | 12 -
target/ppc/cpu.h | 2 +-
target/riscv/cpu.h | 4 +-
target/rx/cpu.h | 5 -
target/s390x/cpu.h | 2 +-
target/sh4/cpu.h | 10 -
target/sparc/cpu.h | 69 +-
target/sparc/helper.h | 116 ++-
target/tricore/cpu.h | 5 -
target/xtensa/cpu.h | 5 -
accel/tcg/cputlb.c | 22 +-
linux-user/sparc/cpu_loop.c | 2 +-
linux-user/sparc/signal.c | 14 +-
semihosting/uaccess.c | 2 +-
target/alpha/cpu.c | 6 +
target/alpha/translate.c | 2 +-
target/arm/cpu.c | 6 +
target/arm/helper.c | 2 +-
target/arm/tcg/helper-a64.c | 4 +-
target/arm/tcg/mte_helper.c | 18 +-
target/arm/tcg/sve_helper.c | 8 +-
target/arm/tcg/tlb_helper.c | 2 +-
target/avr/cpu.c | 6 +
target/cris/cpu.c | 6 +
target/cris/translate.c | 14 +-
target/hppa/cpu.c | 12 +
target/hppa/mem_helper.c | 2 +-
target/hppa/op_helper.c | 8 +-
target/i386/cpu.c | 10 +
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu.c | 11 +
target/loongarch/tcg/tlb_helper.c | 8 +-
target/loongarch/tcg/translate.c | 2 +-
target/m68k/cpu.c | 6 +
target/m68k/op_helper.c | 2 +-
target/microblaze/cpu.c | 18 +-
target/microblaze/helper.c | 3 +-
target/microblaze/mmu.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/cpu.c | 6 +
target/mips/sysemu/physaddr.c | 2 +-
target/mips/tcg/msa_helper.c | 10 +-
target/mips/tcg/sysemu/cp0_helper.c | 2 +-
target/mips/tcg/sysemu/special_helper.c | 2 +-
target/mips/tcg/sysemu/tlb_helper.c | 34 +-
target/nios2/cpu.c | 7 +
target/nios2/translate.c | 2 +-
target/openrisc/cpu.c | 13 +
target/openrisc/translate.c | 2 +-
target/ppc/cpu_init.c | 8 +-
target/ppc/mem_helper.c | 10 +-
target/ppc/mmu_common.c | 4 +-
target/riscv/cpu.c | 6 +
target/riscv/cpu_helper.c | 6 +-
target/riscv/op_helper.c | 4 +-
target/riscv/vector_helper.c | 9 +-
target/rx/cpu.c | 6 +
target/s390x/cpu.c | 6 +
target/s390x/tcg/mem_helper.c | 34 +-
target/sh4/cpu.c | 16 +
target/sparc/cpu.c | 61 +-
target/sparc/fop_helper.c | 510 +++++++------
target/sparc/gdbstub.c | 8 +-
target/sparc/ldst_helper.c | 5 +-
target/sparc/machine.c | 36 +-
target/sparc/mmu_helper.c | 2 +-
target/sparc/translate.c | 799 +++++++--------------
target/tricore/cpu.c | 6 +
target/tricore/helper.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/cpu.c | 6 +
target/xtensa/mmu_helper.c | 2 +-
accel/tcg/ldst_common.c.inc | 42 +-
target/cris/translate_v10.c.inc | 6 +-
.../tcg/insn_trans/trans_privileged.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
tests/tcg/multiarch/gdbstub/prot-none.py | 2 +-
93 files changed, 1060 insertions(+), 1191 deletions(-)
- [PULL 00/57] tcg patch queue,
Richard Henderson <=
- [PULL 01/57] include/hw/core: Add mmu_index to CPUClass, Richard Henderson, 2024/02/02
- [PATCH] linux-user/aarch64: Add padding before __kernel_rt_sigreturn, Richard Henderson, 2024/02/02
- [PULL 02/57] target/alpha: Split out alpha_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 03/57] target/alpha: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 04/57] target/arm: Split out arm_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 05/57] target/arm: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 06/57] target/avr: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 07/57] target/cris: Cache mem_index in DisasContext, Richard Henderson, 2024/02/02
- [PULL 08/57] target/cris: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 09/57] target/hppa: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02