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[PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in d
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5) |
Date: |
Sat, 20 Jan 2024 00:22:59 +0100 |
Code movement to ease review, no logical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/s390x/tcg/translate.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index aedce85029..fd1138c684 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -910,12 +910,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,
uint32_t mask)
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(1);
break;
- case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
- cond = TCG_COND_EQ;
- c->u.s32.a = tcg_temp_new_i32();
- c->u.s32.b = tcg_constant_i32(0);
- tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
- break;
case 0x8 | 0x4: /* cc < 2 */
cond = TCG_COND_LTU;
c->u.s32.b = tcg_constant_i32(2);
@@ -924,6 +918,18 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,
uint32_t mask)
cond = TCG_COND_EQ;
c->u.s32.b = tcg_constant_i32(0);
break;
+ case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
+ cond = TCG_COND_NE;
+ c->u.s32.a = tcg_temp_new_i32();
+ c->u.s32.b = tcg_constant_i32(0);
+ tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
+ break;
+ case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
+ cond = TCG_COND_EQ;
+ c->u.s32.a = tcg_temp_new_i32();
+ c->u.s32.b = tcg_constant_i32(0);
+ tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
+ break;
case 0x4 | 0x2 | 0x1: /* cc != 0 */
cond = TCG_COND_NE;
c->u.s32.b = tcg_constant_i32(0);
@@ -932,12 +938,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,
uint32_t mask)
cond = TCG_COND_GTU;
c->u.s32.b = tcg_constant_i32(1);
break;
- case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
- cond = TCG_COND_NE;
- c->u.s32.a = tcg_temp_new_i32();
- c->u.s32.b = tcg_constant_i32(0);
- tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
- break;
default:
/* CC is masked by something else: (8 >> cc) & mask. */
cond = TCG_COND_NE;
--
2.41.0
- [PATCH v3 18/38 1/2] tcg/aarch64: Massage tcg_out_brcond(), (continued)
- [PATCH v3 13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc, Richard Henderson, 2024/01/10
- [PATCH v3 15/38] target/s390x: Improve general case of disas_jcc, Richard Henderson, 2024/01/10
- [PATCH v3 15/38 1/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (1/5), Philippe Mathieu-Daudé, 2024/01/19
- [PATCH v3 15/38 2/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (2/5), Philippe Mathieu-Daudé, 2024/01/19
- [PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5),
Philippe Mathieu-Daudé <=
- [PATCH v3 15/38 4/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (4/5), Philippe Mathieu-Daudé, 2024/01/19
- [PATCH v3 15/38 5/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (5/5), Philippe Mathieu-Daudé, 2024/01/19
- [PATCH v3 15/38 6/6] target/s390x: Improve general case of disas_jcc, Philippe Mathieu-Daudé, 2024/01/19
- [PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2024/01/10
- [PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond, Richard Henderson, 2024/01/10
- [PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX, Richard Henderson, 2024/01/10