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[PULL 06/65] target/riscv/cpu.c: fix machine IDs getters
From: |
Alistair Francis |
Subject: |
[PULL 06/65] target/riscv/cpu.c: fix machine IDs getters |
Date: |
Wed, 10 Jan 2024 18:56:34 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
mvendorid is an uint32 property, mimpid/marchid are uint64 properties.
But their getters are returning bools. The reason this went under the
radar for this long is because we have no code using the getters.
The problem can be seem via the 'qom-get' API though. Launching QEMU
with the 'veyron-v1' CPU, a model with:
VEYRON_V1_MVENDORID: 0x61f (1567)
VEYRON_V1_MIMPID: 0x111 (273)
VEYRON_V1_MARCHID: 0x8000000000010000 (9223372036854841344)
This is what the API returns when retrieving these properties:
(qemu) qom-get /machine/soc0/harts[0] mvendorid
true
(qemu) qom-get /machine/soc0/harts[0] mimpid
true
(qemu) qom-get /machine/soc0/harts[0] marchid
true
After this patch:
(qemu) qom-get /machine/soc0/harts[0] mvendorid
1567
(qemu) qom-get /machine/soc0/harts[0] mimpid
273
(qemu) qom-get /machine/soc0/harts[0] marchid
9223372036854841344
Fixes: 1e34150045 ("target/riscv/cpu.c: restrict 'mvendorid' value")
Fixes: a1863ad368 ("target/riscv/cpu.c: restrict 'mimpid' value")
Fixes: d6a427e2c0 ("target/riscv/cpu.c: restrict 'marchid' value")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231211170732.2541368-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b07a76ef6b..53b82cc581 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1570,9 +1570,9 @@ static void cpu_set_mvendorid(Object *obj, Visitor *v,
const char *name,
static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- bool value = RISCV_CPU(obj)->cfg.mvendorid;
+ uint32_t value = RISCV_CPU(obj)->cfg.mvendorid;
- visit_type_bool(v, name, &value, errp);
+ visit_type_uint32(v, name, &value, errp);
}
static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
@@ -1599,9 +1599,9 @@ static void cpu_set_mimpid(Object *obj, Visitor *v, const
char *name,
static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- bool value = RISCV_CPU(obj)->cfg.mimpid;
+ uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
- visit_type_bool(v, name, &value, errp);
+ visit_type_uint64(v, name, &value, errp);
}
static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
@@ -1649,9 +1649,9 @@ static void cpu_set_marchid(Object *obj, Visitor *v,
const char *name,
static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- bool value = RISCV_CPU(obj)->cfg.marchid;
+ uint64_t value = RISCV_CPU(obj)->cfg.marchid;
- visit_type_bool(v, name, &value, errp);
+ visit_type_uint64(v, name, &value, errp);
}
static void riscv_cpu_class_init(ObjectClass *c, void *data)
--
2.43.0
- [PULL 00/65] riscv-to-apply queue, Alistair Francis, 2024/01/10
- [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions, Alistair Francis, 2024/01/10
- [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check, Alistair Francis, 2024/01/10
- [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew, Alistair Francis, 2024/01/10
- [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV, Alistair Francis, 2024/01/10
- [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32, Alistair Francis, 2024/01/10
- [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters,
Alistair Francis <=
- [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32, Alistair Francis, 2024/01/10
- [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64, Alistair Francis, 2024/01/10
- [PULL 09/65] target/riscv/kvm: change timer regs size to u64, Alistair Francis, 2024/01/10
- [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong(), Alistair Francis, 2024/01/10
- [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location, Alistair Francis, 2024/01/10
- [PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location, Alistair Francis, 2024/01/10
- [PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG(), Alistair Francis, 2024/01/10
- [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT, Alistair Francis, 2024/01/10
- [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public, Alistair Francis, 2024/01/10
- [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC, Alistair Francis, 2024/01/10