Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking

[Deepak Gupta]

On Fri, Jan 05, 2024 at 10:29:35AM +0300, Alexey Baturo wrote:
> > +    addr = addr << pmlen;
> > +    if (signext) {
> > +        addr = (target_long)addr >> pmlen;
> > +    } else {
> > +        addr = addr >> pmlen;
> Could you please elaborate a bit more on your concern here?
> I believe this code works as intended: https://godbolt.org/z/b9c7na13a
Nevermind I missed this above in code.
addr = addr << pmlen;

You're good. Sorry about that.
> Thanks
>
> пт, 5 янв. 2024 г. в 04:02, Deepak Gupta <debug@rivosinc.com>:
>
> > > --- a/target/riscv/vector_helper.c
> > > +++ b/target/riscv/vector_helper.c
> > > @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc,
> > uint32_t log2_esz)
> > >
> > >  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
> > addr)
> > >  {
> > > +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> > > +    if (pmm == PMM_FIELD_DISABLED)
> > > +        return addr;
> > > +    int pmlen = riscv_pm_get_pmlen(pmm);
> > > +    bool signext = !riscv_cpu_bare_mode(env);
> > > +    addr = addr << pmlen;
> > > +    /* sign/zero extend masked address by N-1 bit */
> > > +    if (signext) {
> > > +        addr = (target_long)addr >> pmlen;
> >
> > These look like right shift operations and not sign extensions of N-1 bit
> >
> > > +    } else {
> > > +        addr = addr >> pmlen;
> >
> > Same here.
> >
> > > +    }
> > >      return addr;
> > >  }
> > >
> > > --
> > > 2.34.1
> > >
> > >