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[PULL 02/46] target/i386: optimize computation of JL and JLE from flags
From: |
Paolo Bonzini |
Subject: |
[PULL 02/46] target/i386: optimize computation of JL and JLE from flags |
Date: |
Sun, 31 Dec 2023 09:44:18 +0100 |
Take advantage of the fact that there can be no 1 bits between SF and OF.
If they were adjacent, you could sum SF and get a carry only if SF was
already set. Then the value of OF in the sum is the XOR of OF itself,
the carry (which is SF) and 0 (the value of the OF bit in the addend):
this is OF^SF exactly.
Because OF and SF are not adjacent, just place more 1 bits to the
left so that the carry propagates, which means summing CC_O - CC_S.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 037bc47e7c2..8fb80011a22 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1126,10 +1126,9 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
if (reg == cpu_cc_src) {
reg = s->tmp0;
}
- tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
- tcg_gen_xor_tl(reg, reg, cpu_cc_src);
+ tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
- .mask = CC_S };
+ .mask = CC_O };
break;
default:
case JCC_LE:
@@ -1137,10 +1136,9 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
if (reg == cpu_cc_src) {
reg = s->tmp0;
}
- tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
- tcg_gen_xor_tl(reg, reg, cpu_cc_src);
+ tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
- .mask = CC_S | CC_Z };
+ .mask = CC_O | CC_Z };
break;
}
break;
--
2.43.0
- [PULL 00/46] (mostly) target/i386 and meson changes for 2023-12-31, Paolo Bonzini, 2023/12/31
- [PULL 01/46] configure: use a native non-cross compiler for linux-user, Paolo Bonzini, 2023/12/31
- [PULL 02/46] target/i386: optimize computation of JL and JLE from flags,
Paolo Bonzini <=
- [PULL 05/46] target/i386: remove unnecessary truncations, Paolo Bonzini, 2023/12/31
- [PULL 07/46] target/i386: document more deviations from the manual, Paolo Bonzini, 2023/12/31
- [PULL 03/46] target/i386: speedup JO/SETO after MUL or IMUL, Paolo Bonzini, 2023/12/31
- [PULL 04/46] target/i386: remove unnecessary arguments from raise_interrupt, Paolo Bonzini, 2023/12/31
- [PULL 06/46] target/i386: clean up cpu_cc_compute_all, Paolo Bonzini, 2023/12/31
- [PULL 08/46] target/i386: reimplement check for validity of LOCK prefix, Paolo Bonzini, 2023/12/31
- [PULL 09/46] target/i386: avoid trunc and ext for MULX and RORX, Paolo Bonzini, 2023/12/31
- [PULL 10/46] target/i386: rename zext0/zext2 and make them closer to the manual, Paolo Bonzini, 2023/12/31
- [PULL 11/46] target/i386: add X86_SPECIALs for MOVSX and MOVZX, Paolo Bonzini, 2023/12/31
- [PULL 14/46] target/i386: do not clobber T0 on string operations, Paolo Bonzini, 2023/12/31