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[PULL 45/71] hw/pci-bridge: Constify VMState
From: |
Richard Henderson |
Subject: |
[PULL 45/71] hw/pci-bridge: Constify VMState |
Date: |
Sat, 30 Dec 2023 08:23:20 +1100 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231221031652.119827-46-richard.henderson@linaro.org>
---
hw/pci-bridge/gen_pcie_root_port.c | 2 +-
hw/pci-bridge/i82801b11.c | 2 +-
hw/pci-bridge/ioh3420.c | 2 +-
hw/pci-bridge/pci_bridge_dev.c | 2 +-
hw/pci-bridge/pcie_pci_bridge.c | 2 +-
hw/pci-bridge/xio3130_downstream.c | 2 +-
hw/pci-bridge/xio3130_upstream.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/pci-bridge/gen_pcie_root_port.c
b/hw/pci-bridge/gen_pcie_root_port.c
index 1ce4e7beba..784507c826 100644
--- a/hw/pci-bridge/gen_pcie_root_port.c
+++ b/hw/pci-bridge/gen_pcie_root_port.c
@@ -117,7 +117,7 @@ static const VMStateDescription vmstate_rp_dev = {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index 0e83cd11b2..c140919cbc 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -81,7 +81,7 @@ err_bridge:
static const VMStateDescription i82801b11_bridge_dev_vmstate = {
.name = "i82801b11_bridge",
.priority = MIG_PRI_PCI_BUS,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
VMSTATE_END_OF_LIST()
}
diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
index f1e16135a3..be752a4bda 100644
--- a/hw/pci-bridge/ioh3420.c
+++ b/hw/pci-bridge/ioh3420.c
@@ -88,7 +88,7 @@ static const VMStateDescription vmstate_ioh3420 = {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
index 4b2696ea7f..089f91efed 100644
--- a/hw/pci-bridge/pci_bridge_dev.c
+++ b/hw/pci-bridge/pci_bridge_dev.c
@@ -199,7 +199,7 @@ static bool pci_device_shpc_present(void *opaque, int
version_id)
static const VMStateDescription pci_bridge_dev_vmstate = {
.name = "pci_bridge",
.priority = MIG_PRI_PCI_BUS,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),
VMSTATE_END_OF_LIST()
diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c
index 2301b2ca0b..7646ac2397 100644
--- a/hw/pci-bridge/pcie_pci_bridge.c
+++ b/hw/pci-bridge/pcie_pci_bridge.c
@@ -132,7 +132,7 @@ static Property pcie_pci_bridge_dev_properties[] = {
static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
.name = TYPE_PCIE_PCI_BRIDGE_DEV,
.priority = MIG_PRI_PCI_BUS,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
SHPC_VMSTATE(shpc, PCIDevice, NULL),
VMSTATE_END_OF_LIST()
diff --git a/hw/pci-bridge/xio3130_downstream.c
b/hw/pci-bridge/xio3130_downstream.c
index 38a2361fa2..907d5105b0 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -146,7 +146,7 @@ static const VMStateDescription vmstate_xio3130_downstream
= {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index a48bfe3bc5..2a6cff6e03 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -115,7 +115,7 @@ static const VMStateDescription vmstate_xio3130_upstream = {
.priority = MIG_PRI_PCI_BUS,
.version_id = 1,
.minimum_version_id = 1,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort),
VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
vmstate_pcie_aer_log, PCIEAERLog),
--
2.34.1
- [PULL 35/71] hw/ipack: Constify VMState, (continued)
- [PULL 35/71] hw/ipack: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 37/71] hw/isa: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 38/71] hw/loongarch: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 39/71] hw/m68k: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 40/71] hw/misc: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 41/71] hw/net: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 43/71] hw/openrisc: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 42/71] hw/nvram: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 47/71] hw/ppc: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 44/71] hw/pci: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 45/71] hw/pci-bridge: Constify VMState,
Richard Henderson <=
- [PULL 46/71] hw/pci-host: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 48/71] hw/riscv: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 49/71] hw/rtc: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 50/71] hw/s390x: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 52/71] hw/sd: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 53/71] hw/sensor: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 51/71] hw/scsi: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 54/71] hw/sparc: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 55/71] hw/ssi: Constify VMState, Richard Henderson, 2023/12/29
- [PULL 56/71] hw/timer: Constify VMState, Richard Henderson, 2023/12/29