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[RFC v1 0/2] RISC-V: ACPI: Enable SPCR
From: |
Sia Jee Heng |
Subject: |
[RFC v1 0/2] RISC-V: ACPI: Enable SPCR |
Date: |
Thu, 28 Dec 2023 16:06:14 +0800 |
This series focuses on enabling the Serial Port Console Redirection (SPCR)
table for the RISC-V virt platform. Considering that ARM utilizes the same
function, the initial patch involves migrating the build_spcr function to
common code. This consolidation ensures that RISC-V avoids duplicating the
function.
The patch set is built upon Alistair's riscv-to-apply.next branch and
relies on Sunil's patches at [1].
[1]
20231218150247.466427-1-sunilvl@ventanamicro.com/">https://lore.kernel.org/qemu-devel/20231218150247.466427-1-sunilvl@ventanamicro.com/
Sia Jee Heng (2):
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
hw/riscv/virt-acpi-build.c: Generate SPCR table
hw/acpi/aml-build.c | 51 ++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 68 +++++++++++++++----------------------
hw/riscv/virt-acpi-build.c | 39 +++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 33 ++++++++++++++++++
include/hw/acpi/aml-build.h | 4 +++
5 files changed, 154 insertions(+), 41 deletions(-)
--
2.34.1
- [RFC v1 0/2] RISC-V: ACPI: Enable SPCR,
Sia Jee Heng <=