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[PATCH 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] |
Date: |
Thu, 21 Dec 2023 14:51:37 -0300 |
Keep all class properties in riscv_cpu_properties[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 110 +++++++++++++++++++++++----------------------
1 file changed, 57 insertions(+), 53 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a5607bf1d0..0bcaf7818c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1930,6 +1930,62 @@ const PropertyInfo prop_mimpid = {
.set = prop_mimpid_set,
};
+static void prop_marchid_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ uint64_t prev_val = cpu->cfg.marchid;
+ uint64_t value, invalid_val;
+ uint32_t mxlen = 0;
+
+ if (!visit_type_uint64(v, name, &value, errp)) {
+ return;
+ }
+
+ if (!dynamic_cpu && prev_val != value) {
+ error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
+ object_get_typename(obj), prev_val);
+ return;
+ }
+
+ switch (riscv_cpu_mxl(&cpu->env)) {
+ case MXL_RV32:
+ mxlen = 32;
+ break;
+ case MXL_RV64:
+ case MXL_RV128:
+ mxlen = 64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ invalid_val = 1LL << (mxlen - 1);
+
+ if (value == invalid_val) {
+ error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
+ "and the remaining bits zero", mxlen);
+ return;
+ }
+
+ cpu->cfg.marchid = value;
+}
+
+static void prop_marchid_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint64_t value = RISCV_CPU(obj)->cfg.marchid;
+
+ visit_type_uint64(v, name, &value, errp);
+}
+
+const PropertyInfo prop_marchid = {
+ .name = "marchid",
+ .get = prop_marchid_get,
+ .set = prop_marchid_set,
+};
+
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
@@ -1956,6 +2012,7 @@ static Property riscv_cpu_properties[] = {
{.name = "mvendorid", .info = &prop_mvendorid},
{.name = "mimpid", .info = &prop_mimpid},
+ {.name = "marchid", .info = &prop_marchid},
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
@@ -2021,56 +2078,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
- RISCVCPU *cpu = RISCV_CPU(obj);
- uint64_t prev_val = cpu->cfg.marchid;
- uint64_t value, invalid_val;
- uint32_t mxlen = 0;
-
- if (!visit_type_uint64(v, name, &value, errp)) {
- return;
- }
-
- if (!dynamic_cpu && prev_val != value) {
- error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
- object_get_typename(obj), prev_val);
- return;
- }
-
- switch (riscv_cpu_mxl(&cpu->env)) {
- case MXL_RV32:
- mxlen = 32;
- break;
- case MXL_RV64:
- case MXL_RV128:
- mxlen = 64;
- break;
- default:
- g_assert_not_reached();
- }
-
- invalid_val = 1LL << (mxlen - 1);
-
- if (value == invalid_val) {
- error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
- "and the remaining bits zero", mxlen);
- return;
- }
-
- cpu->cfg.marchid = value;
-}
-
-static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint64_t value = RISCV_CPU(obj)->cfg.marchid;
-
- visit_type_uint64(v, name, &value, errp);
-}
-
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -2101,9 +2108,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
- cpu_set_marchid, NULL, NULL);
-
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.43.0
- [PATCH 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[], (continued)
- [PATCH 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 07/16] target/riscv: rework 'vext_spec', Daniel Henrique Barboza, 2023/12/21
- [PATCH 09/16] target/riscv: move 'elen' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 10/16] target/riscv: create finalize_features() for KVM, Daniel Henrique Barboza, 2023/12/21
- [PATCH 11/16] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 12/16] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 13/16] target/riscv: remove riscv_cpu_options[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 15/16] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 14/16] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[],
Daniel Henrique Barboza <=