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[PATCH 07/16] target/riscv: rework 'vext_spec'
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 07/16] target/riscv: rework 'vext_spec' |
Date: |
Thu, 21 Dec 2023 14:51:28 -0300 |
The same rework did in 'priv_spec' is done for 'vext_spec'. This time is
simpler, since we only accept one value ("v1.0") and we'll always have
env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to
convert string to 'vext_ver' back and forth like we needed for
'priv_spec'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 42 ++++++++++++++++++++++++++++++++++----
target/riscv/cpu.h | 1 +
target/riscv/cpu_cfg.h | 1 -
target/riscv/tcg/tcg-cpu.c | 15 --------------
4 files changed, 39 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e1813eca7..05ca458177 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1237,6 +1237,8 @@ static void riscv_cpu_post_init(Object *obj)
static void riscv_cpu_init(Object *obj)
{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
@@ -1249,8 +1251,11 @@ static void riscv_cpu_init(Object *obj)
* for all CPUs. Each accelerator will decide what to do when
* users disable them.
*/
- RISCV_CPU(obj)->cfg.ext_zicntr = true;
- RISCV_CPU(obj)->cfg.ext_zihpm = true;
+ cpu->cfg.ext_zicntr = true;
+ cpu->cfg.ext_zihpm = true;
+
+ /* vext_spec is always 1_00_0 */
+ cpu->env.vext_ver = VEXT_VERSION_1_00_0;
}
typedef struct misa_ext_info {
@@ -1629,9 +1634,37 @@ const PropertyInfo prop_priv_spec = {
.set = prop_priv_spec_set,
};
-Property riscv_cpu_options[] = {
- DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ g_autofree char *value = NULL;
+
+ visit_type_str(v, name, &value, errp);
+
+ if (!g_strcmp0(value, VEXT_VER_1_00_0_STR)) {
+ error_setg(errp, "Unsupported vector spec version '%s'", value);
+ return;
+ }
+
+ cpu->env.vext_ver = VEXT_VERSION_1_00_0;
+}
+
+static void prop_vext_spec_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const char *value = VEXT_VER_1_00_0_STR;
+ visit_type_str(v, name, (char **)&value, errp);
+}
+
+const PropertyInfo prop_vext_spec = {
+ .name = "vext_spec",
+ .get = prop_vext_spec_get,
+ .set = prop_vext_spec_set,
+};
+
+Property riscv_cpu_options[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
@@ -1652,6 +1685,7 @@ static Property riscv_cpu_properties[] = {
{.name = "pmp", .info = &prop_pmp},
{.name = "priv_spec", .info = &prop_priv_spec},
+ {.name = "vext_spec", .info = &prop_vext_spec},
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e8a691ca63..53101b82c5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,6 +89,7 @@ enum {
};
#define VEXT_VERSION_1_00_0 0x00010000
+#define VEXT_VER_1_00_0_STR "v1.0"
enum {
TRANSLATE_SUCCESS,
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 2dba1f0007..7112af6c4c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -135,7 +135,6 @@ struct RISCVCPUConfig {
bool ext_XVentanaCondOps;
uint32_t pmu_mask;
- char *vext_spec;
uint16_t vlen;
uint16_t elen;
uint16_t cbom_blocksize;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 4d67b72d9e..6501c29d8e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -201,21 +201,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env,
RISCVCPUConfig *cfg,
"in the range [8, 64]");
return;
}
-
- if (cfg->vext_spec) {
- if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
- env->vext_ver = VEXT_VERSION_1_00_0;
- } else {
- error_setg(errp, "Unsupported vector spec version '%s'",
- cfg->vext_spec);
- return;
- }
- } else if (env->vext_ver == 0) {
- qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-
- env->vext_ver = VEXT_VERSION_1_00_0;
- }
}
static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
--
2.43.0
- [PATCH 00/16] target/riscv: deprecate riscv_cpu_options[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 01/16] target/riscv/cpu_cfg.h: remove user_spec and bext_spec, Daniel Henrique Barboza, 2023/12/21
- [PATCH 02/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 04/16] target/riscv: move 'mmu' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 03/16] target/riscv: make riscv_cpu_is_generic() public, Daniel Henrique Barboza, 2023/12/21
- [PATCH 05/16] target/riscv: move 'pmp' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 06/16] target/riscv: rework 'priv_spec', Daniel Henrique Barboza, 2023/12/21
- [PATCH 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 07/16] target/riscv: rework 'vext_spec',
Daniel Henrique Barboza <=
- [PATCH 09/16] target/riscv: move 'elen' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 10/16] target/riscv: create finalize_features() for KVM, Daniel Henrique Barboza, 2023/12/21
- [PATCH 11/16] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 12/16] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 13/16] target/riscv: remove riscv_cpu_options[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 15/16] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 14/16] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21
- [PATCH 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[], Daniel Henrique Barboza, 2023/12/21