Move the old_scr2 variable to NeXTPC so that the old SCR2 register state is
stored along with the current SCR2 state.
Since the SCR2 register is 32-bits wide, convert old_scr2 to uint32_t and
update the SCR2 register access code to allow unaligned writes.
Note that this is a migration break, but as nothing will currently boot then
we do not need to worry about this now.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/next-cube.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
index 7ffd1c412e..fd707b4b54 100644
--- a/hw/m68k/next-cube.c
+++ b/hw/m68k/next-cube.c
@@ -91,6 +91,7 @@ struct NeXTPC {
uint32_t scr1;
uint32_t scr2;
+ uint32_t old_scr2;
uint32_t int_mask;
uint32_t int_status;
uint32_t led;
@@ -137,8 +138,7 @@ static void next_scr2_led_update(NeXTPC *s)
static void nextscr2_write(NeXTPC *s, uint32_t val, int size)
{
- static uint8_t old_scr2;
- uint8_t scr2_2;
+ uint8_t old_scr2, scr2_2;
NextRtc *rtc = &s->rtc;
if (size == 4) {
@@ -147,6 +147,8 @@ static void nextscr2_write(NeXTPC *s, uint32_t val, int
size)
scr2_2 = val & 0xFF;
}
+ old_scr2 = (s->old_scr2 >> 8) & 0xff;
+
if (scr2_2 & 0x1) {
/* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */
if (rtc->phase == -1) {
@@ -255,7 +257,6 @@ static void nextscr2_write(NeXTPC *s, uint32_t val, int
size)
}
s->scr2 = val & 0xFFFF00FF;
s->scr2 |= scr2_2 << 8;
- old_scr2 = scr2_2;
}
static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size)
@@ -321,8 +322,11 @@ static void next_mmio_write(void *opaque, hwaddr addr,
uint64_t val,
break;
case 0xd000 ... 0xd003:
+ s->scr2 = deposit32(s->scr2, (4 - (addr - 0xd000) - size) << 3,
+ size << 3, val);
next_scr2_led_update(s);
nextscr2_write(s, val, size);
+ s->old_scr2 = s->scr2;
break;