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[PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit()
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From: |
Daniel Henrique Barboza |
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Subject: |
[PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit() |
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Date: |
Mon, 18 Dec 2023 09:53:30 -0300 |
Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit.
The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check
the first CPU of a given hart array, not any given CPU.
Create a helper to retrieve the info for any given CPU, not the first
CPU of the hart array. The helper is using the same 32 bit check that
riscv_cpu_satp_mode_finalize() was doing.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 7 ++++++-
target/riscv/cpu.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6af1148cf5..1dea5db52d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -53,6 +53,11 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD,
RVV,
#define BYTE(x) (x)
#endif
+bool riscv_cpu_is_32bit(RISCVCPU *cpu)
+{
+ return riscv_cpu_mxl(&cpu->env) == MXL_RV32;
+}
+
#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
{#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
@@ -980,7 +985,7 @@ static void riscv_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
{
- bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
+ bool rv32 = riscv_cpu_is_32bit(cpu);
uint8_t satp_mode_map_max, satp_mode_supported_max;
/* The CPU wants the OS to decide which satp mode to use */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1f34eda1e4..485d2da3c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -695,6 +695,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
void riscv_cpu_update_mask(CPURISCVState *env);
+bool riscv_cpu_is_32bit(RISCVCPU *cpu);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
--
2.43.0
- [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash, (continued)
- [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 14/26] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 15/26] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 16/26] target/riscv/tcg: validate profiles during finalize, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 17/26] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 18/26] target/riscv: add 'rva22u64' CPU, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 19/26] target/riscv: implement svade, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 21/26] target/riscv/cpu.c: finalize satp_mode earlier, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit(),
Daniel Henrique Barboza <=
- [PATCH v13 20/26] target/riscv: add priv ver restriction to profiles, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 23/26] target/riscv: add satp_mode profile support, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 24/26] target/riscv: add 'parent' in profile description, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 25/26] target/riscv: add RVA22S64 profile, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 26/26] target/riscv: add rva22s64 cpu, Daniel Henrique Barboza, 2023/12/18