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[PATCH v13 05/26] target/riscv: add zicbop extension flag
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v13 05/26] target/riscv: add zicbop extension flag |
Date: |
Mon, 18 Dec 2023 09:53:13 -0300 |
QEMU already implements zicbom (Cache Block Management Operations) and
zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv:
add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for
what would be the instructions for zicbop (Cache Block Prefetch
Operations), which are now no-ops.
The RVA22U64 profile mandates zicbop, which means that applications that
run with this profile might expect zicbop to be present in the riscv,isa
DT and might behave badly if it's absent.
Adding zicbop as an extension will make our future RVA22U64
implementation more in line with what userspace expects and, if/when
cache block prefetch operations became relevant to QEMU, we already have
the extension flag to turn then on/off as needed.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
hw/riscv/virt.c | 5 +++++
target/riscv/cpu.c | 3 +++
target/riscv/cpu_cfg.h | 2 ++
3 files changed, 10 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d2eac24156..da650865e5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -273,6 +273,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_ptr->cfg.cboz_blocksize);
}
+ if (cpu_ptr->cfg.ext_zicbop) {
+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size",
+ cpu_ptr->cfg.cbop_blocksize);
+ }
+
qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 34102f6869..86e3514cc8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -78,6 +78,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD,
RVV,
*/
const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
+ ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
@@ -1376,6 +1377,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
+ MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true),
MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
@@ -1510,6 +1512,7 @@ Property riscv_cpu_options[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+ DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64),
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index f4605fb190..bd2ff87cc8 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -65,6 +65,7 @@ struct RISCVCPUConfig {
bool ext_zicntr;
bool ext_zicsr;
bool ext_zicbom;
+ bool ext_zicbop;
bool ext_zicboz;
bool ext_zicond;
bool ext_zihintntl;
@@ -142,6 +143,7 @@ struct RISCVCPUConfig {
uint16_t vlen;
uint16_t elen;
uint16_t cbom_blocksize;
+ uint16_t cbop_blocksize;
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
--
2.43.0
- [PATCH v13 00/26] riscv: RVA22 profiles support, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 01/26] target/riscv: create TYPE_RISCV_VENDOR_CPU, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 02/26] target/riscv/tcg: do not use "!generic" CPU checks, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 03/26] target/riscv/tcg: update priv_ver on user_set extensions, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 04/26] target/riscv: add rv64i CPU, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 05/26] target/riscv: add zicbop extension flag,
Daniel Henrique Barboza <=
- [PATCH v13 06/26] target/riscv/tcg: add 'zic64b' support, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 07/26] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 08/26] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 09/26] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 10/26] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 14/26] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/12/18
- [PATCH v13 15/26] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/12/18