[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 35/35] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1
From: |
Peter Maydell |
Subject: |
[PATCH 35/35] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs |
Date: |
Mon, 18 Dec 2023 11:33:05 +0000 |
Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for
the Neoverse N2 and Neoverse V1 CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu.c | 5 -----
target/arm/tcg/cpu64.c | 2 +-
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index d827b42de79..f67aea2d836 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -64,6 +64,7 @@ the following architecture extensions:
- FEAT_MTE2 (Memory Tagging Extension)
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
- FEAT_NV (Nested Virtualization)
+- FEAT_NV2 (Enhanced nested virtualization support)
- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)
- FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm)
- FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d1d592609eb..65dc88ba864 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2243,11 +2243,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
cpu->isar.id_aa64pfr0 =
FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
- /* FEAT_NV2 (Enhanced Nested Virtualization support) */
- if (FIELD_EX64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV) > 1) {
- cpu->isar.id_aa64mmfr2 =
- FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 1);
- }
}
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 93f040e6e96..5fba2c0f040 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1204,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
- t = FIELD_DP64(t, ID_AA64MMFR2, NV, 1); /* FEAT_NV */
+ t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */
t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
--
2.34.1
- Re: [PATCH 27/35] target/arm: Report VNCR_EL2 based faults correctly, (continued)
- [PATCH 28/35] target/arm: Mark up VNCR offsets (offsets 0x0..0xff), Peter Maydell, 2023/12/18
- [PATCH 29/35] target/arm: Mark up VNCR offsets (offsets 0x100..0x160), Peter Maydell, 2023/12/18
- [PATCH 31/35] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC), Peter Maydell, 2023/12/18
- [PATCH 21/35] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs, Peter Maydell, 2023/12/18
- [PATCH 35/35] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs,
Peter Maydell <=
- [PATCH 30/35] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8), Peter Maydell, 2023/12/18
- [PATCH 32/35] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers, Peter Maydell, 2023/12/18
- [PATCH 34/35] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry, Peter Maydell, 2023/12/18
- [PATCH 33/35] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps, Peter Maydell, 2023/12/18
- Re: [PATCH 00/35] target/arm: Implement emulation of nested virtualization, Miguel Luis, 2023/12/22