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[PATCH 04/35] target/arm: Handle HCR_EL2 accesses for bits introduced wi
From: |
Peter Maydell |
Subject: |
[PATCH 04/35] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV |
Date: |
Mon, 18 Dec 2023 11:32:34 +0000 |
FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the
feature is enabled, allow these bits to be written, and flush the
TLBs for the bits which affect page table interpretation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-features.h | 5 +++++
target/arm/helper.c | 6 +++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 954d3582685..3a43c328d9e 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -839,6 +839,11 @@ static inline bool isar_feature_aa64_e0pd(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
}
+static inline bool isar_feature_aa64_nv(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0;
+}
+
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 39830c7f948..ca8de414bdb 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5799,6 +5799,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_rme, cpu)) {
valid_mask |= HCR_GPF;
}
+ if (cpu_isar_feature(aa64_nv, cpu)) {
+ valid_mask |= HCR_NV | HCR_NV1 | HCR_AT;
+ }
}
if (cpu_isar_feature(any_evt, cpu)) {
@@ -5817,9 +5820,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
* HCR_DC disables stage1 and enables stage2 translation
* HCR_DCT enables tagging on (disabled) stage1 translation
* HCR_FWB changes the interpretation of stage2 descriptor bits
+ * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
*/
if ((env->cp15.hcr_el2 ^ value) &
- (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) {
+ (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB | HCR_NV | HCR_NV1)) {
tlb_flush(CPU(cpu));
}
env->cp15.hcr_el2 = value;
--
2.34.1
- [PATCH 00/35] target/arm: Implement emulation of nested virtualization, Peter Maydell, 2023/12/18
- [PATCH 01/35] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only, Peter Maydell, 2023/12/18
- [PATCH 03/35] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers, Peter Maydell, 2023/12/18
- [PATCH 04/35] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV,
Peter Maydell <=
- [PATCH 05/35] target/arm: Implement HCR_EL2.AT handling, Peter Maydell, 2023/12/18
- [PATCH 02/35] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU, Peter Maydell, 2023/12/18
- [PATCH 06/35] target/arm: Enable trapping of ERET for FEAT_NV, Peter Maydell, 2023/12/18
- [PATCH 07/35] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set, Peter Maydell, 2023/12/18
- [PATCH 08/35] target/arm: Allow use of upper 32 bits of TBFLAG_A64, Peter Maydell, 2023/12/18