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[PATCH 26/33] hw/arm/fsl-imx7: Let the A7MPcore create/wire the CPU core
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 26/33] hw/arm/fsl-imx7: Let the A7MPcore create/wire the CPU cores |
Date: |
Tue, 12 Dec 2023 17:29:26 +0100 |
Set the properties on the a7mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/fsl-imx7.h | 4 ---
hw/arm/fsl-imx7.c | 62 +++++----------------------------------
hw/arm/mcimx7d-sabre.c | 3 +-
3 files changed, 10 insertions(+), 59 deletions(-)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index a6f3a96029..77771f916c 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -36,7 +36,6 @@
#include "hw/net/imx_fec.h"
#include "hw/pci-host/designware.h"
#include "hw/usb/chipidea.h"
-#include "cpu.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -63,11 +62,8 @@ enum FslIMX7Configuration {
};
struct FslIMX7State {
- /*< private >*/
DeviceState parent_obj;
- /*< public >*/
- ARMCPU cpu[FSL_IMX7_NUM_CPUS];
CortexMPPrivState a7mpcore;
IMXGPTState gpt[FSL_IMX7_NUM_GPTS];
IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS];
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index bd9266b8b5..f71ffe7910 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -26,25 +26,16 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
+#include "target/arm/cpu.h" /* qom */
#define NAME_SIZE 20
static void fsl_imx7_init(Object *obj)
{
- MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(obj);
char name[NAME_SIZE];
int i;
- /*
- * CPUs
- */
- for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
- snprintf(name, NAME_SIZE, "cpu%d", i);
- object_initialize_child(obj, name, &s->cpu[i],
- ARM_CPU_TYPE_NAME("cortex-a7"));
- }
-
/*
* A7MPCORE
*/
@@ -163,7 +154,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(dev);
DeviceState *gic;
- Object *o;
int i;
qemu_irq irq;
char name[NAME_SIZE];
@@ -175,56 +165,20 @@ static void fsl_imx7_realize(DeviceState *dev, Error
**errp)
return;
}
- /*
- * CPUs
- */
- for (i = 0; i < smp_cpus; i++) {
- o = OBJECT(&s->cpu[i]);
-
- /* On uniprocessor, the CBAR is set to 0 */
- if (smp_cpus > 1) {
- object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR,
- &error_abort);
- }
-
- if (i) {
- /*
- * Secondary CPUs start in powered-down state (and can be
- * powered up via the SRC system reset controller)
- */
- object_property_set_bool(o, "start-powered-off", true,
- &error_abort);
- }
-
- qdev_realize(DEVICE(o), NULL, &error_abort);
- }
-
/*
* A7MPCORE
*/
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cores", smp_cpus,
- &error_abort);
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
- FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
-
+ qdev_prop_set_uint32(DEVICE(&s->a7mpcore), "num-cores", ms->smp.cpus);
+ qdev_prop_set_string(DEVICE(&s->a7mpcore), "cpu-type",
+ ARM_CPU_TYPE_NAME("cortex-a7"));
+ qdev_prop_set_uint64(DEVICE(&s->a7mpcore), "cpu-reset-cbar",
+ FSL_IMX7_A7MPCORE_ADDR);
+ qdev_prop_set_uint32(DEVICE(&s->a7mpcore), "gic-spi-num",
+ FSL_IMX7_MAX_IRQ + GIC_INTERNAL);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
gic = DEVICE(&s->a7mpcore);
- for (i = 0; i < smp_cpus; i++) {
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(qemu_get_cpu(i));
-
- irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
- sysbus_connect_irq(sbd, i, irq);
- irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
- sysbus_connect_irq(sbd, i + smp_cpus, irq);
- irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
- sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
- irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
- sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
- }
-
/*
* A7MPCORE DAP
*/
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 693a1023b6..782f7591db 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -20,6 +20,7 @@
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
+#include "target/arm/cpu.h" /* qom */
static void mcimx7d_sabre_init(MachineState *machine)
{
@@ -64,7 +65,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->cpu[0], machine, &boot_info);
+ arm_load_kernel(s->a7mpcore.cpu[0], machine, &boot_info);
}
}
--
2.41.0
- [PATCH 16/33] hw/cpu/arm: Handle GIC once in MPCore parent, (continued)
- [PATCH 16/33] hw/cpu/arm: Handle GIC once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 17/33] hw/cpu/arm: Document more properties of CORTEX_MPCORE_PRIV QOM type, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 19/33] hw/cpu/arm: Introduce TYPE_A7MPCORE_PRIV for Cortex-A7 MPCore, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 18/33] hw/cpu/arm: Replace A15MPPrivState by CortexMPPrivState, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 21/33] hw/cpu/arm: Create CPUs once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 22/33] hw/arm/aspeed_ast2600: Let the A7MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 20/33] hw/cpu/arm: Consolidate check on max GIC spi supported, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 23/33] hw/arm/exynos4210: Let the A9MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 24/33] hw/arm/fsl-imx6: Let the A9MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 25/33] hw/arm/fsl-imx6ul: Let the A7MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 26/33] hw/arm/fsl-imx7: Let the A7MPcore create/wire the CPU cores,
Philippe Mathieu-Daudé <=
- [PATCH 27/33] hw/arm/highbank: Let the A9/A15MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 28/33] hw/arm/vexpress: Let the A9/A15MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 29/33] hw/arm/xilinx_zynq: Let the A9MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 31/33] hw/cpu/a9mpcore: Remove legacy code, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 30/33] hw/arm/npcm7xx: Let the A9MPcore create/wire the CPU cores, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 32/33] hw/cpu/arm: Remove 'num-cpu' property alias, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 33/33] hw/cpu/arm: Remove use of qemu_get_cpu() in A7/A15 realize(), Philippe Mathieu-Daudé, 2023/12/12
- Re: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv, Philippe Mathieu-Daudé, 2023/12/26