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[PATCH v2 1/5] sysemu/cpu-timers: Introduce ICountMode enumerator
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 1/5] sysemu/cpu-timers: Introduce ICountMode enumerator |
Date: |
Thu, 7 Dec 2023 16:45:46 +0100 |
Rather than having to lookup for what the 0, 1, 2, ...
icount values are, use a enum definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/sysemu/cpu-timers.h | 20 +++++++++++++-------
accel/tcg/icount-common.c | 16 +++++++---------
stubs/icount.c | 2 +-
system/cpu-timers.c | 2 +-
target/arm/helper.c | 3 ++-
5 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/include/sysemu/cpu-timers.h b/include/sysemu/cpu-timers.h
index 2e786fe7fb..e909ffae47 100644
--- a/include/sysemu/cpu-timers.h
+++ b/include/sysemu/cpu-timers.h
@@ -17,18 +17,24 @@ void cpu_timers_init(void);
/* icount - Instruction Counter API */
-/*
- * icount enablement state:
+/**
+ * ICountMode: icount enablement state:
*
- * 0 = Disabled - Do not count executed instructions.
- * 1 = Enabled - Fixed conversion of insn to ns via "shift" option
- * 2 = Enabled - Runtime adaptive algorithm to compute shift
+ * @ICOUNT_DISABLED: Disabled - Do not count executed instructions.
+ * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" option
+ * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shift
*/
+typedef enum {
+ ICOUNT_DISABLED = 0,
+ ICOUNT_PRECISE = 1,
+ ICOUNT_ADAPTATIVE = 2,
+} ICountMode;
+
#ifdef CONFIG_TCG
-extern int use_icount;
+extern ICountMode use_icount;
#define icount_enabled() (use_icount)
#else
-#define icount_enabled() 0
+#define icount_enabled() ICOUNT_DISABLED
#endif
/*
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index ec57192be8..067c93a9ae 100644
--- a/accel/tcg/icount-common.c
+++ b/accel/tcg/icount-common.c
@@ -49,21 +49,19 @@ static bool icount_sleep = true;
/* Arbitrarily pick 1MIPS as the minimum allowable speed. */
#define MAX_ICOUNT_SHIFT 10
-/*
- * 0 = Do not count executed instructions.
- * 1 = Fixed conversion of insn to ns via "shift" option
- * 2 = Runtime adaptive algorithm to compute shift
- */
-int use_icount;
+/* Do not count executed instructions */
+ICountMode use_icount = ICOUNT_DISABLED;
static void icount_enable_precise(void)
{
- use_icount = 1;
+ /* Fixed conversion of insn to ns via "shift" option */
+ use_icount = ICOUNT_PRECISE;
}
static void icount_enable_adaptive(void)
{
- use_icount = 2;
+ /* Runtime adaptive algorithm to compute shift */
+ use_icount = ICOUNT_ADAPTATIVE;
}
/*
@@ -256,7 +254,7 @@ static void icount_warp_rt(void)
int64_t warp_delta;
warp_delta = clock - timers_state.vm_clock_warp_start;
- if (icount_enabled() == 2) {
+ if (icount_enabled() == ICOUNT_ADAPTATIVE) {
/*
* In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too far
* ahead of real time (it might already be ahead so careful not
diff --git a/stubs/icount.c b/stubs/icount.c
index 6df8c2bf7d..f8e6a014b8 100644
--- a/stubs/icount.c
+++ b/stubs/icount.c
@@ -4,7 +4,7 @@
/* icount - Instruction Counter API */
-int use_icount;
+ICountMode use_icount = ICOUNT_DISABLED;
void icount_update(CPUState *cpu)
{
diff --git a/system/cpu-timers.c b/system/cpu-timers.c
index 7452d97b67..6befb82e48 100644
--- a/system/cpu-timers.c
+++ b/system/cpu-timers.c
@@ -154,7 +154,7 @@ static bool adjust_timers_state_needed(void *opaque)
static bool icount_shift_state_needed(void *opaque)
{
- return icount_enabled() == 2;
+ return icount_enabled() == ICOUNT_ADAPTATIVE;
}
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2746d3fdac..adb0960bba 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -934,7 +934,8 @@ static int64_t cycles_ns_per(uint64_t cycles)
static bool instructions_supported(CPUARMState *env)
{
- return icount_enabled() == 1; /* Precise instruction counting */
+ /* Precise instruction counting */
+ return icount_enabled() == ICOUNT_PRECISE;
}
static uint64_t instructions_get_count(CPUARMState *env)
--
2.41.0
[PATCH v2 4/5] system/vl: Restrict icount to TCG emulation, Philippe Mathieu-Daudé, 2023/12/07