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[PATCH qemu v3 06/20] Fixing the basic functionality of STM32 timers


From: ~lbryndza
Subject: [PATCH qemu v3 06/20] Fixing the basic functionality of STM32 timers
Date: Sat, 02 Dec 2023 13:13:59 +0100

From: Lucjan Bryndza <lbryndza.oss@icloud.com>

The current implementation of timers does not work properly
even in basic functionality. A counter configured to report
an interrupt every 10ms reports the first interrupts after a
few seconds.  There are also no properly implemented count up an
count down modes. This commit fixes bugs with interrupt
reporting and implements the basic modes of the counter's
time-base block.

Add timer update UIF

Signed-off-by: Lucjan Bryndza <lbryndza.oss@icloud.com>
---
 hw/timer/stm32f2xx_timer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 62c98b5f04..bd3d1bcf24 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -90,6 +90,12 @@ static void stm32f2xx_timer_update(STM32F2XXTimerState *s)
     }
 }
 
+static void stm32f2xx_timer_update_uif(STM32F2XXTimerState *s, uint8_t value)
+{
+    s->tim_sr &= ~TIM_SR1_UIF;
+    s->tim_sr |= (value & TIM_SR1_UIF);
+    qemu_set_irq(s->irq, value);
+}
 
 static void stm32f2xx_timer_reset(DeviceState *dev)
 {
-- 
2.38.5




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