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[PATCH 1/2] target/riscv: FIX xATP_MODE validation
From: |
Irina Ryapolova |
Subject: |
[PATCH 1/2] target/riscv: FIX xATP_MODE validation |
Date: |
Fri, 1 Dec 2023 14:53:38 +0300 |
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR
fields are only defined
for a subset of bit encodings, but allow any value to be written while
guaranteeing to return a legal
value whenever read (See riscv-privileged-20211203, SATP CSR).
For example on rv64 we are trying to write to SATP CSR val = 0x1000000000000000
(SATP_MODE = 1 - Reserved for standard use)
and after that we are trying to read SATP_CSR. We read from the SATP CSR value
= 0x1000000000000000, which is not a correct
operation (return illegal value).
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fde7ce1a53..6f244815b7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1278,8 +1278,8 @@ static RISCVException read_mstatus(CPURISCVState *env,
int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- return (vm & 0xf) <=
- satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
+ uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.supported;
+ return get_field(mode_supported, (1 << vm));
}
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
--
2.25.1
- [PATCH 1/2] target/riscv: FIX xATP_MODE validation,
Irina Ryapolova <=