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[PULL 05/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no ov
From: |
Peter Maydell |
Subject: |
[PULL 05/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow |
Date: |
Mon, 6 Nov 2023 15:32:31 +0000 |
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
We support only 3- and 4-level page-tables, which is firstly checked in
vtd_decide_config(), then setup in vtd_init(). Than level fields are
checked by vtd_is_level_supported().
So here we can't have level out from 1..4 inclusive range. Let's assert
it. That also explains Coverity that we are not going to overflow the
array.
CID: 1487158, 1487186
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
Message-id: 20231017125941.810461-2-vsementsov@yandex-team.ru
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/i386/intel_iommu.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 1c6c18622fd..1a44ef696c3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1045,18 +1045,35 @@ static dma_addr_t
vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
* Rsvd field masks for spte:
* vtd_spte_rsvd 4k pages
* vtd_spte_rsvd_large large pages
+ *
+ * We support only 3-level and 4-level page tables (see vtd_init() which
+ * sets only VTD_CAP_SAGAW_39bit and maybe VTD_CAP_SAGAW_48bit bits in s->cap).
*/
-static uint64_t vtd_spte_rsvd[5];
-static uint64_t vtd_spte_rsvd_large[5];
+#define VTD_SPTE_RSVD_LEN 5
+static uint64_t vtd_spte_rsvd[VTD_SPTE_RSVD_LEN];
+static uint64_t vtd_spte_rsvd_large[VTD_SPTE_RSVD_LEN];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
- uint64_t rsvd_mask = vtd_spte_rsvd[level];
+ uint64_t rsvd_mask;
+
+ /*
+ * We should have caught a guest-mis-programmed level earlier,
+ * via vtd_is_level_supported.
+ */
+ assert(level < VTD_SPTE_RSVD_LEN);
+ /*
+ * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=1 and
+ * checked by vtd_is_last_slpte().
+ */
+ assert(level);
if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
(slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
/* large page */
rsvd_mask = vtd_spte_rsvd_large[level];
+ } else {
+ rsvd_mask = vtd_spte_rsvd[level];
}
return slpte & rsvd_mask;
--
2.34.1
- [PULL 00/12] target-arm queue, Peter Maydell, 2023/11/06
- [PULL 01/12] hw/arm/virt: fix PMU IRQ registration, Peter Maydell, 2023/11/06
- [PULL 03/12] hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables., Peter Maydell, 2023/11/06
- [PULL 11/12] hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0, Peter Maydell, 2023/11/06
- [PULL 04/12] tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references, Peter Maydell, 2023/11/06
- [PULL 07/12] mc146818rtc: rtc_set_time(): initialize tm to zeroes, Peter Maydell, 2023/11/06
- [PULL 05/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow,
Peter Maydell <=
- [PULL 06/12] util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow, Peter Maydell, 2023/11/06
- [PULL 10/12] io/channel-socket: qio_channel_socket_flush(): improve msg validation, Peter Maydell, 2023/11/06
- [PULL 09/12] hw/core/loader: gunzip(): initialize z_stream, Peter Maydell, 2023/11/06
- [PULL 08/12] block/nvme: nvme_process_completion() fix bound for cid, Peter Maydell, 2023/11/06
- [PULL 02/12] tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2, Peter Maydell, 2023/11/06
- [PULL 12/12] target/arm: Fix A64 LDRA immediate decode, Peter Maydell, 2023/11/06
- Re: [PULL 00/12] target-arm queue, Stefan Hajnoczi, 2023/11/06