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[PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first
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From: |
Alistair Francis |
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Subject: |
[PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first |
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Date: |
Fri, 8 Sep 2023 16:03:32 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bc9e151aa9..379f03df06 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -584,7 +584,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, offset, PAGE_READ)) {
+ if (!page_check_range(addr, offset, PAGE_READ)) {
vl = i;
goto ProbeSuccess;
}
--
2.41.0
- [PULL 00/65] riscv-to-apply queue, Alistair Francis, 2023/09/08
- [PULL 01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG, Alistair Francis, 2023/09/08
- [PULL 03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts, Alistair Francis, 2023/09/08
- [PULL 02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts, Alistair Francis, 2023/09/08
- [PULL 04/65] target/riscv/cpu.c: add zmmul isa string, Alistair Francis, 2023/09/08
- [PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first,
Alistair Francis <=
- [PULL 07/65] target/riscv: Use existing lookup tables for MixColumns, Alistair Francis, 2023/09/08
- [PULL 05/65] target/riscv/cpu.c: add smepmp isa string, Alistair Francis, 2023/09/08
- [PULL 08/65] target/riscv: Refactor some of the generic vector functionality, Alistair Francis, 2023/09/08
- [PULL 09/65] target/riscv: Refactor vector-vector translation macro, Alistair Francis, 2023/09/08
- [PULL 12/65] target/riscv: Move vector translation checks, Alistair Francis, 2023/09/08
- [PULL 10/65] target/riscv: Remove redundant "cpu_vl == 0" checks, Alistair Francis, 2023/09/08
- [PULL 11/65] target/riscv: Add Zvbc ISA extension support, Alistair Francis, 2023/09/08
- [PULL 13/65] target/riscv: Refactor translation of vector-widening instruction, Alistair Francis, 2023/09/08
- [PULL 14/65] target/riscv: Refactor some of the generic vector functionality, Alistair Francis, 2023/09/08
- [PULL 15/65] target/riscv: Add Zvbb ISA extension support, Alistair Francis, 2023/09/08